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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
16:15		 Oita B-ConPlaza An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders
Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75		 In recent years, high speed and high precision computing is increasingly needed.
Hardware support for IEEE754 compliant... [more]		 CPSY2014-75
pp.19-23
SCE 2009-10-20
13:50		 Tokyo Kikai-Shinko-Kaikan Bldg. Design of SFQ Floating-Point Units Using Nb Advanced Process
Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Nat. Univ.), Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) SCE2009-19		 We are developing a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which ... [more] SCE2009-19
pp.13-18
SCE 2008-01-25
15:45		 Tokyo Kikai-Shinko-Kaikan Bldg. Design and implementation of the SFQ half-precision floating point adder
Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Koji Obata, Yuki Itou, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) 		A new project was started to develop a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SF... [more] SCE2007-31
pp.35-40
NLP 2007-03-06
10:15		 Miyagi   Resistive ladder D/A converters for floating-point representation
Hiroyuki Tomura, Toshimichi Saito (Hosei Univ.) 		This paper presents a circuit model of a floating-point resistive ladder D/A converter.
In the circuit, the mantissa i... [more]		 NLP2006-157
pp.17-20
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