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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| VLD | 2014-03-04 10:45 |
Okinawa | Okinawa Seinen Kaikan | An Approach of Rate-Distortion Optimized Quantization and its Evaluation Genki Moriguchi, Hajime Sawano, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.) VLD2013-145 |
Rate-distortion optimized quantization (RDOQ) is becoming a popular technology to improve its video coding performance. ... [more] |
VLD2013-145 pp.67-72 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 14:50 |
Kanagawa | Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool Yoshihiro Nakamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-133 CPSY2012-82 RECONF2012-87 |
In this paper, we implemented a stencil computation kernel on an FPGA accelerator using MaxCompiler and MaxGenFD tools, ... [more] | VLD2012-133 CPSY2012-82 RECONF2012-87 pp.153-158 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 11:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-61 DC2012-27 |
With process technology scaling, heat problems in IC chips as well as increasing the average interconnection delays are ... [more] | VLD2012-61 DC2012-27 pp.13-18 |
| IPSJ-SLDM, VLD | 2012-05-30 14:55 |
Fukuoka | Kitakyushu International Conference Center | Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-2 |
HDR architecture has been proposed as a platform that integrates energy-efficiency and interconnection delays into high-... [more] | VLD2012-2 pp.7-12 |
| ICD, VLD | 2007-03-09 14:20 |
Okinawa | Mielparque Okinawa | A behavioral power modeling algorithm which considers area speed tradeoff Noriyuki Inoue, Masaaki Ohtsuki, Masahiro Fukui (Ritsumeikan Uni.) |
Due to the rapid growth of the size of systems, it has become a very important task to plan the design strategy based on... [more] | VLD2006-151 ICD2006-242 pp.63-68 |
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 15:00 |
Miyagi | Ichinobo, Sakunami-Spa | A study for power and speed tradeoff estimation for behavior hardware model Noriyuki Inoue, Katsuhiro Oshikawa, Tomonori Izumi, Masahiro Fukui (Rits Univ.) |
Due to the increasing of the scale of systems, planning the design strategy based on the power estimation in early desig... [more] | SIP2005-126 ICD2005-145 IE2005-90 pp.67-72 |
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