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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2023-03-25 14:05 |
Kagoshima |
Amagi Town Disaster Prevention Center (Tokunoshima) (Primary: On-site, Secondary: Online) |
Design of Decoded Instruction Cache Takero Magara, Nobuyuki Yamasaki (Keio Univ.) CPSY2022-52 DC2022-111 |
In Intel x86 processors, instructions are decoded into instructions for the internal RISC engine, called Micro-Operation... [more] |
CPSY2022-52 DC2022-111 pp.106-111 |
CPSY, DC, IPSJ-ARC [detail] |
2020-07-30 11:00 |
Online |
Online |
Instruction Prefetcher focusing on properties of Prefetch Distance Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya (UTokyo) CPSY2020-1 DC2020-1 |
Instruction cache misses and branch target buffer (BTB) misses are performance bottlenecks in recent applications,
and ... [more] |
CPSY2020-1 DC2020-1 pp.1-8 |
RECONF |
2019-05-09 12:35 |
Tokyo |
Tokyo Tech Front |
Efficient Instruction Fetch Architectures for a RISC-V Soft Processor Hiromu Miyazaki, Junya Miura, Kenji Kise (Tokyo Tech) RECONF2019-1 |
We aim to develop a cost-effective RISC-V scalar processor of pipelining for FPGAs. In this report, we try to implement ... [more] |
RECONF2019-1 pp.1-6 |
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] |
2015-03-07 09:45 |
Kagoshima |
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Energy Reduction of BTB by focusing on Number of Branches per Cache Line Hiroki Yamamoto, Ryotaro Kobayashi (TUT), Hajime Shimada (NU) CPSY2014-177 DC2014-103 |
Recent processors exploit Instruction Level Parallelism to improve performance, but it's limited by control dependency. ... [more] |
CPSY2014-177 DC2014-103 pp.89-94 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] |
2010-03-28 11:15 |
Tokyo |
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Design and Evaluation of An Instruction Scheduler for FU Array Processor Kazuhiro Yoshimura, Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2009-94 DC2009-91 |
Recently, we have proposed Linear Array Pipeline Processor (LAPP) that improves energy efficiency for various workloads ... [more] |
CPSY2009-94 DC2009-91 pp.511-516 |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-30 12:45 |
Kanagawa |
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A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-116 CPSY2008-78 RECONF2008-80 |
In this paper, we propose an energy-efficient ASIP synthesis method based on reducing instruction memory access. Since a... [more] |
VLD2008-116 CPSY2008-78 RECONF2008-80 pp.147-152 |
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