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All Technical Committee Conferences (Searched in: All Years)
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| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| RECONF |
2011-09-26
10:45 |
Aichi |
Nagoya Univ. |
Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1.
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications)  RECONF2011-22 |
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] |
RECONF2011-22
pp.1-6 |
| RECONF |
2011-05-13
10:45 |
Hokkaido |
Hokkaido Univ. (Faculty of Eng., B3 Bldg.) |
Optimization of Application Programs of SLD-1 : A Low Power Accelarator
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] |
RECONF2011-15
pp.85-90 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18
14:50 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Silent Large Datapath : A Ultra Low Power Accelarater
Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78 |
Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded
systems. By using a... [more] |
VLD2010-109 CPSY2010-64 RECONF2010-78
pp.169-174 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18
15:10 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79 |
Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] |
VLD2010-110 CPSY2010-65 RECONF2010-79
pp.175-180 |
| CS, IPSJ-AVM, ITE-BCT, IE [detail] |
2010-12-02
11:15 |
Kyoto |
Nagoya Univ |
A Study of a CSMA/CA Access Method Using Code-Division Cell Systems
Daisuke Ikebuchi, Satoru Aikawa (Univ. of Hyogo) CS2010-54 IE2010-93 |
Recently, the systems having a cluster mobility such as vehicle groups are considered. It is difficult to cope with a cl... [more] |
CS2010-54 IE2010-93
pp.17-22 |
| VLD |
2010-03-11
14:35 |
Okinawa |
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A Break Even Time Prediction of Run-Time Power Gating Circuits by an On-chip Leakage Monitor using an MTCMOS circuit
Satoshi Koyama, Tatsunori Hashida, Kimiyoshi Usami (Shibaura Inst. of Tech.), Daisuke Ikebuchi, Hideharu Amano (Keio Univ.) VLD2009-114 |
[more] |
VLD2009-114
pp.91-96 |
| ICD, IPSJ-ARC, IPSJ-EMB |
2009-01-14
13:45 |
Osaka |
Shoushin Kaikan |
Fine-Grained Dynamic Sleep Control on the Combination of High-Perfomance Cores and Low-Power Cores
Naomi Seki, Lei Zhao, Daisuke Ikebuchi, Yu Kojima, Hideharu Amano (Keio Univ) |
[more] |
ICD2008-143
pp.81-86 |
| ICD, IPSJ-ARC |
2008-05-14
15:30 |
Tokyo |
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A Fine Grain Dynamic Sleep Control Scheme in Superscalar Processor
Yu Kojima, Daisuke Ikebuchi, Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.), Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami (Shibaura Inst of Tech), Tetsuya Sunada, Jun Kanai, Mitaro Namiki (Tokyo Univ. of Agri & Tech), Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
Geyser-0 is a low power MIPS R3000 processor which uses a novel fine grain power gating technique to computational units... [more] |
ICD2008-33
pp.87-92 |
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