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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2024-03-22 09:50 |
Nagasaki |
Ikinoshima Hall (Primary: On-site, Secondary: Online) |
Integration of Vector Extension and Simultaneous Multithreading for a RISC-V Processor Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) CPSY2023-43 DC2023-109 |
In vector architectures, the potential for parallel execution lies in the chaining of instruction sequences. However, a ... [more] |
CPSY2023-43 DC2023-109 pp.29-34 |
RECONF |
2023-09-14 16:20 |
Tokyo |
Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Integrating RISC-V Vector Extension and SMT for Embedded AI Workloads Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) RECONF2023-22 |
In this paper, we plan to implement a processor that accelerates AI workloads by integrating RISC-V vector extensions th... [more] |
RECONF2023-22 pp.13-14 |
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] |
2022-01-24 14:50 |
Online |
Online |
Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65 |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] |
VLD2021-57 CPSY2021-26 RECONF2021-65 pp.43-48 |
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