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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 13:20 |
Kanagawa | Hiyoshi Campus, Keio University | A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT)  VLD2013-126 CPSY2013-97 RECONF2013-80 |
Recently, a scalable and reconfigurable multi-FPGA system has been proposed which consists of two or more boards, each ... [more] |
VLD2013-126 CPSY2013-97 RECONF2013-80 pp.143-148 |
| EST | 2013-05-10 15:50 |
Kanagawa | NTT Science and Core Technology Laboratory Group | Comparison of Fixed Point and Floating Point Calculations for parallel processing of FDTD method using FPGA Ryota Takasu, Tempei Hasegawa, Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Tsugumichi Shibata, Mamoru Nakanishi (NTT), Hitoshi Kitazawa (Tokyo Univ. of Agriculture and Tech.) EST2013-9 |
In this paper, we discuss the advantages and disadvantages of fixed point and floating point arithmetic calculations of ... [more] | EST2013-9 pp.45-50 |
| VLD | 2012-03-06 13:10 |
Oita | B-con Plaza | 10G/1G dual-rate EPON OLT LSI with dual encryption modes selected using DBA-information-based algorithm control Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT) VLD2011-124 |
For next-generation optical access systems, we developed a 10G/1G dual-rate EPON OLT LSI that fully conforms to the IEEE... [more] | VLD2011-124 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki | NewWelCity Miyazaki | A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT) CPM2011-166 ICD2011-98 |
A multifunctional bridge function unit and buffer function unit were developed for the OLT LSI for the coexistence of 10... [more] | CPM2011-166 ICD2011-98 pp.91-96 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 11:20 |
Miyazaki | NewWelCity Miyazaki | 10G-EPON OLT and ONU LSIs for next-generation FTTx system Tomoaki Kawamura, Shoko Ohteru, Sadayuki Yasuda, Akihiko Miyazaki, Kenji Kawai, Ritsu Kusaba, Mamoru Nakanishi, Masami Urano, Tsugumichi Shibata (NTT) CPM2011-167 ICD2011-99 |
10G-EPON OLT and ONU LSIs that integrate the full functions confirming to the IEEE 802.3av standard were developed for n... [more] | CPM2011-167 ICD2011-99 pp.97-102 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 10:45 |
Fukuoka | Kyushu University | FPGA design and test methodology for communication frame processinng Ritsu Kusaba, Kenji Kawai, Sadayuki Yasuda, Satoshi Shigematsu, Mamoru Nakanishi, Masami Urano (NTT) VLD2010-67 DC2010-34 |
For large-scale and high-speed frame processing on a ＦＰＧＡ board, we propose a new design method based on the property of... [more] | VLD2010-67 DC2010-34 pp.73-78 |
| VLD | 2009-03-12 11:05 |
Okinawa | High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit Naoki Miura, Satoshi Shigematsu, Takahiro Hatano (NTT), Yusuke Akamine (Kyushu Univ.), Mamoru Nakanishi, Masami Urano (NTT) VLD2008-143 |
(To be available after the conference date) [more] | VLD2008-143 pp.101-106 |
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