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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-28
13:30		 Oita B-ConPlaza [Invited Talk] A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS
Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.) VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45		 To meet ever-increasing demands for computing power in data centers, data rates over 50Gbps/signal (e.g., OIF CEI-56G-VS... [more] VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45
pp.167-172(VLD), pp.27-32(CPM), pp.27-32(ICD), pp.69-74(CPSY), pp.167-172(DC), pp.63-68(RECONF)
SDM, ICD 2013-08-02
14:25		 Ishikawa Kanazawa University [Invited Talk] A 10th Generation 16-Core SPARC64 Processor for Mission-Critical UNIX Server
Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi (Fujitsu), Yoichi Koyanagi (Fujitsu Laboratories), Ryuji Iwatsuki, Kazumi Hayasaka (Fujitsu), Taiki Uemura (Fujitsu Semiconductor), Gaku Itou, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada (Fujitsu) SDM2013-83 ICD2013-65		 A 10th generation SPARC64 processor is fabricated in enhanced 28nm CMOS process. It runs at 3.0GHz and contains 16 cores... [more] SDM2013-83 ICD2013-65
pp.95-98
ICD, ITE-IST 2013-07-04
10:55		 Hokkaido San Refre Hakodate [Invited Talk] 32 Gb/s Data-Interpolator Receiver with 2-tap DFE in 28-nm CMOS
Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida (Fujitsu Lab. Ltd.), Hiroki Miyaoka (FSL), Masanori Hoshino (FMSL), Yoichi Koyanagi (Fujitsu Lab. Ltd.), Takuji Yamamoto (FLA), Sanroku Tsukamoto, Hirotaka Tamura (Fujitsu Lab. Ltd.) ICD2013-27		 We present a 32Gb/s data-interpolator receiver for electrical chip-to-chip communications. The receiver front-end is clo... [more] ICD2013-27
pp.19-24
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