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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 26  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2024-03-23
09:50
Nagasaki Ikinoshima Hall
(Primary: On-site, Secondary: Online)
An Efficient and Secure Data Transfer Method for Large Data between Host and Enclave on Keystone Enclave
Akihiro Saiki, Keiji Kimura (Waseda Univ.) CPSY2023-49 DC2023-115
Keystone Enclave, one of the TEE implementations in RISC-V, lacks flexibility in data transfer between the host and the ... [more] CPSY2023-49 DC2023-115
pp.65-70
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2024-03-23
11:45
Nagasaki Ikinoshima Hall
(Primary: On-site, Secondary: Online)
Evaluating composition of quantum circuit and learnability in quantum neural network with NISQ devices
Naoki Marumo (Waseda Univ.), Yasutaka Wada (Meisei Univ.), Kazunori Ueda, Keiji Kimura (Waseda Univ.) CPSY2023-52 DC2023-118
The more numbers of repeat of Ansatz and the more qubit entangling improve learnability of quantum machine learning by v... [more] CPSY2023-52 DC2023-118
pp.82-87
CPSY, DC, IPSJ-ARC [detail] 2023-08-03
16:00
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
Extension of Enclave Application Cache to RISC-V Keystone
Takumu Umezawa, Akihiro Saiki, Keiji Kimura (Waseda univ.) CPSY2023-15 DC2023-15
The development of the IoT society and the spread of cloud computing have also led to an increase in devices with inadeq... [more] CPSY2023-15 DC2023-15
pp.43-48
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2023-03-23
13:25
Kagoshima Amagi Town Disaster Prevention Center (Tokunoshima)
(Primary: On-site, Secondary: Online)
A Flexible and Efficient Data Transfer Method between Host and Enclave in Isolated Execution Environments Using Fat Pointers and Memory Pools
Nozomi Yamamoto, Yu Omori, Keiji Kimura (Waseda Univ.) CPSY2022-35 DC2022-94
Various OS vulnerabilities have been reported so far, and the reliability of the OS as an execution environment for prog... [more] CPSY2022-35 DC2022-94
pp.7-12
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2023-03-23
16:25
Kagoshima Amagi Town Disaster Prevention Center (Tokunoshima)
(Primary: On-site, Secondary: Online)
Evaluation of Bit-Reduced Homomorphic Encryption Library on Intel Xeon and Fujitsu A64FX
Masaki Nishi, Teppei Shishido, Xinyi Li, Keiji Kimura (Waseda Univ.), Kentaro Sano (RIKEN) CPSY2022-38 DC2022-97
As deep learning is used in various applications, the protection of training data, input data, inference results, and tr... [more] CPSY2022-38 DC2022-97
pp.25-30
DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2023-03-23
17:15
Kagoshima Amagi Town Disaster Prevention Center (Tokunoshima)
(Primary: On-site, Secondary: Online)
Preliminary Evaluation of Low Power Optimized ORB-SLAM3 on Jetson Xavier NX
Raito Hayashi (Waseda Univ.), Hiroki Mikami, Akira Nodomi (Oscar Tech.), Sadahiro Kimura (NSITEXE,Inc.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2022-40 DC2022-99
 [more] CPSY2022-40 DC2022-99
pp.37-42
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
15:45
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Acceleration of HE-Transformer with bit reduced SEAL and HEXL
Xinyi Li, Masaki Nishi, Teppei Shishido, Keiji Kimura (Waseda Univ.) CPSY2022-12 DC2022-12
While cloud applications are covering people's privacy data, their related risks, such as theft risk, leak risk, and oth... [more] CPSY2022-12 DC2022-12
pp.65-70
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-11
09:30
Online Online LocalMapping Parallelization and CPU Allocation Method on ORB-SLAM3
Kazuki Yamamoto, Takugo Osakabe, Honoka Koike, Tohma Kawasumi, Kazuki Fujita, Toshiaki Kitamura (Waseda Univ.), Akihiro Kawashima, Akira Nodomi (Oscar Tech.), Sadahiro Kimura (NSITEXE,Inc.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2021-58 DC2021-92
(To be available after the conference date) [more] CPSY2021-58 DC2021-92
pp.79-84
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-11
10:30
Online Online Acceleration of Homomorphic Encryption Library SEAL by Reducing the Number of Arithmetic Bits
Teppei Shishido, Masaki Nishi, Xinyi LI, Keiji Kimura (Waseda Univ.) CPSY2021-60 DC2021-94
(To be available after the conference date) [more] CPSY2021-60 DC2021-94
pp.91-96
CPSY, DC, IPSJ-ARC [detail] 2021-07-20
14:00
Online Online Prototype Implementation of Non-Volatile Memory Support for RISC-V Keystone Enclave
Lena Yu, Yu Omori, Keiji Kimura (Waseda Univ.) CPSY2021-2 DC2021-2
Handling confidential information has become an increasingly important concern among many areas of society. However, cur... [more] CPSY2021-2 DC2021-2
pp.7-12
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-25
14:40
Online Online Parallelization and Vectorization of SpMM for Sparse Neural Network
Yuta Tadokoro, Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2020-55 DC2020-85
Pruning is one of the well-known model compression techniques in Deep Learning. Eliminating less important weights in th... [more] CPSY2020-55 DC2020-85
pp.31-36
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-27
17:20
Kagoshima Yoron-cho Chuou-Kouminkan Toward acceleration of matrix multiplication on homomorphic encryption library
Tetsuya Makita, Teppei Shishido (Waseda Univ.), Yasutaka Wada (Meisei Univ.), Keiji Kimura (Waseda Univ.) CPSY2019-96 DC2019-102
(To be available after the conference date) [more] CPSY2019-96 DC2019-102
pp.51-56
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-27
16:05
Kagoshima Yoron-cho Chuou-Kouminkan NDCKPT: Transparent Checkpointing on NVDIMM with Operating System Support
Hikaru Nishida, Keiji Kimura (Waseda Univ.) CPSY2019-102 DC2019-108
Checkpointing is a technique to give a fault tolerance to applications. Some research proposed ways to checkpoint arbitr... [more] CPSY2019-102 DC2019-108
pp.87-92
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-28
10:55
Kagoshima Yoron-cho Chuou-Kouminkan Extension of OSCAR Compiler for Parallelizing C++ Programs
Tohma Kawasumi, Tilman Priesner, Masato Noguchi, Jixin Han, Hiroki Mikami (Waseda Univ.), Akihiro Kawashima, Keishiro Tanaka (OscarTechnology Corp.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2019-110 DC2019-116
With the increasing focuses on multicore processors, the OSCAR compiler is known as an automatically parallelizing compi... [more] CPSY2019-110 DC2019-116
pp.151-156
MoNA, IN, CNR
(Joint) [detail]
2018-11-15
10:25
Saga Karatsu Civic Exchange Plaza Integration of repeatable computer system emulator and network simulator
Yuuki Shimizu (Waseda Univ.), Mineo Takai (Osaka Univ.), Keiji Kimura (Waseda Univ.) MoNA2018-22 CNR2018-19
Network simulation combined with a computer system emulator is an attractive approach. It can avoid complex and error-pr... [more] MoNA2018-22 CNR2018-19
pp.1-6(MoNA), pp.7-12(CNR)
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-07
10:20
Kagoshima   Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems
Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami (Waseda Univ.), Uichiro Takahashi, Sakae Inoue (Fujitsu), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2014-178 DC2014-104
This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications... [more] CPSY2014-178 DC2014-104
pp.95-100
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2014-03-16
14:30
Okinawa   A parallelizing compiler cooperative acceleration technique of multicore architecture simulation using a statistical method
Gakuho Taguchi, Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2013-117 DC2013-104
A parallelizing compiler cooperative acceleration technique for multicore architecture simulation is proposed in this pa... [more] CPSY2013-117 DC2013-104
pp.289-294
MSS 2010-01-21
13:25
Aichi Toyota Central R&D Labs. Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme
Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Satoh (Hitachi), Masayoshi Mase, Jun Shirako (Waseda Univ.), Mikiko Sato (Tokyo Univ. of Agr and Tech.), Masashi Takada, Masayuki Ito (Renesas), Hiroyuki Mizuno (Hitachi), Mitaro Namiki (Tokyo Univ. of Agr and Tech.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CST2009-38
We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on ... [more] CST2009-38
pp.7-12
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
11:15
Osaka Shoushin Kaikan Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose core... [more] ICD2008-140
pp.63-68
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
11:45
Osaka Shoushin Kaikan Local Memory Management Scheme by a Compiler for Multicore Processor
Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use o... [more] ICD2008-141
pp.69-74
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