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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 46  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-28
13:00
Kagoshima Yoron-cho Chuou-Kouminkan Design and Post-layout Simulation Verification of PLA Reconfigurable Decoder with General-purpose Logic Switch
Daiki Ishikawa, Nobuyuki Yahiro, Shigetoshi Nakatake (Univ. of Kitakyusyu) CPSY2019-111 DC2019-117
 [more] CPSY2019-111 DC2019-117
pp.171-176
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-28
13:20
Kagoshima Yoron-cho Chuou-Kouminkan DAC-based Multiplier in Analog-digital Mixed-signal Perceptron Circuit
Jinichiro Noguchi, Shigetoshi Nakatake (Univ. of Kitakyushu) CPSY2019-112 DC2019-118
 [more] CPSY2019-112 DC2019-118
pp.177-181
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-17
13:00
Kagoshima Nishinoomote City Hall (Tanega-shima) MOSFET-based ultra high resistance configuration for ultra low current sensing
Xinghuai Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) CPSY2018-103 DC2018-85
In this work, we propose a method to configure an ultrahigh resistance of 1GΩ or more on a chip, which is used for I-V c... [more] CPSY2018-103 DC2018-85
pp.103-108
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-17
13:40
Kagoshima Nishinoomote City Hall (Tanega-shima) On estimation of intravesical urine volume using AC impedance method
Ryosuke Sakai, shigetoshi nakatake (Univ. of Kitakyushu) CPSY2018-105 DC2018-87
In this work, in order to prevent urinary incontinence caused by various functional diseases, we aim to estimate the uri... [more] CPSY2018-105 DC2018-87
pp.115-119
VLD, HWS
(Joint)
2018-03-02
09:00
Okinawa Okinawa Seinen Kaikan On-chip and ultra low current measurement circuit based on potentiostat method
Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2017-119
We propose a current measurement circuit using on - chip high resistance by MOSFET. Due to advances in biosensing techno... [more] VLD2017-119
pp.181-186
VLD, CAS, MSS, SIP 2016-06-17
16:40
Aomori Hirosaki Shiritsu Kanko-kan On Study of Data Reliability of Threshold Sensing with Majority Circuit
Akito Hoshide, Bo Liu, Takuro Ishida, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2016-35 VLD2016-41 SIP2016-69 MSS2016-35
 [more] CAS2016-35 VLD2016-41 SIP2016-69 MSS2016-35
pp.191-196
VLD, CAS, MSS, SIP 2016-06-17
17:00
Aomori Hirosaki Shiritsu Kanko-kan Analog Characterization Module based on A/D and D/A Converters
Daishi Isogai, Bo Liu, Futa Yoshinaka, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2016-36 VLD2016-42 SIP2016-70 MSS2016-36
 [more] CAS2016-36 VLD2016-42 SIP2016-70 MSS2016-36
pp.197-202
VLD, CAS, MSS, SIP 2016-06-17
17:20
Aomori Hirosaki Shiritsu Kanko-kan Soft-Coupling Module with A/D and D/A Converters
Futa Yoshinaka, Bo Liu, Daishi Isogai, Shigetoshi Nakatake (univ.kitakyushu) CAS2016-37 VLD2016-43 SIP2016-71 MSS2016-37
 [more] CAS2016-37 VLD2016-43 SIP2016-71 MSS2016-37
pp.203-208
RCC, ASN, RCS, NS, SR
(Joint)
2015-07-31
09:00
Nagano JA Naganoken Bldg. A sensor-based visualizable auscultatory blood pressure measurement learning support tool
Chooi-Ling Goh (Design Algorithm Laboratory), Shigetoshi Nakatake (Univ. of Kitakyushu) ASN2015-51
In order to help the healthcare practitioners to master the skill of measuring blood pressure by auscultatory method mor... [more] ASN2015-51
pp.177-182
RECONF 2015-06-20
14:25
Kyoto Kyoto University Tile-base PLA Cell with Uni-Switch Structure
Atsushi Nanri, Kosuke Murakami, Daijiro Murooka, Takuya Hirata, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) RECONF2015-23
 [more] RECONF2015-23
pp.125-130
VLD 2015-03-02
14:55
Okinawa Okinawa Seinen Kaikan Symmetrical Routing based on Set-pair Routing and Mixed Integer Programming
Masato Ito, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-157
This paper proposes a routing algorithm of high routability focusing on symmetrical routing used in analog layout. In a ... [more] VLD2014-157
pp.25-30
VLD 2015-03-04
09:15
Okinawa Okinawa Seinen Kaikan On PLL Layouts Evaluation based on Transistor-array Style
Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-175
The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that uni... [more] VLD2014-175
pp.123-128
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:10
Oita B-ConPlaza Analytical placement consistent with hierarchical structure constraints in analog floorplan
Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-73 DC2014-27
 [more] VLD2014-73 DC2014-27
pp.9-13
IE, ICD, VLD, IPSJ-SLDM [detail] 2014-10-02
13:50
Miyagi   Low-power programmable delay element and clock skew tuning by delay locked loop
Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-62 ICD2014-55 IE2014-41
 [more] VLD2014-62 ICD2014-55 IE2014-41
pp.13-18
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-10
15:40
Hokkaido Hokkaido University [Panel Discussion] Management of Technical Committees for Promoting Innovation
Kunihiko Hiraishi (JAIST), Takafumi Yamaji (Toshiba), Shigetoshi Nakatake (Univ. of Kitakyushu), Yoshinobu Kajikawa (Kansai Univ.), Satoshi Yamane (Kanazawa Univ.) CAS2014-32 VLD2014-41 SIP2014-53 MSS2014-32 SIS2014-32
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] CAS2014-32 VLD2014-41 SIP2014-53 MSS2014-32 SIS2014-32
p.169
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-11
13:20
Hokkaido Hokkaido University Block-merge layout of an op-amp pair and its variability evaluation
Masashi Miyagawa, Masaya Shimoyama, Koichi Tanno (Miyazaki Univ.), Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake (Univ. of Kitakyushu), Akihiro Yamada (A.LSI Design Co.,LTD) CAS2014-39 VLD2014-48 SIP2014-60 MSS2014-39 SIS2014-39
 [more] CAS2014-39 VLD2014-48 SIP2014-60 MSS2014-39 SIS2014-39
pp.207-212
VLD, IPSJ-SLDM 2014-05-29
08:30
Fukuoka Kitakyushu International Conference Center Analog Floorplan with Hierarchical Structure Constraints
Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-1
 [more] VLD2014-1
pp.1-6
VLD, IPSJ-SLDM 2014-05-29
08:55
Fukuoka Kitakyushu International Conference Center Characteristics of Programmable Delay Element based on Channel Decomposition
Daijiro Murooka, Koji Nagao, Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-2
 [more] VLD2014-2
pp.7-12
CS, CAS, SIP 2014-03-06
13:50
Osaka Osaka City University Media Center A study on visualization of auscultation-based blood pressure measurement
Nobuhito Ochi, Yusuke Ohtsuka, Yusuke Katsuki, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Hiromi Kodama, Kiyako Takai, Nagisa Okada (Univ. of Occupetional and Environmental Health) CAS2013-107 SIP2013-153 CS2013-120
Blood pressure measurement by Korotkoff sounds auscultation is an essential skill for health care workers, but the skill... [more] CAS2013-107 SIP2013-153 CS2013-120
pp.97-102
IE, ICD, VLD, IPSJ-SLDM [detail] 2013-10-08
11:25
Aomori   A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements
Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) VLD2013-59 ICD2013-83 IE2013-59
Variable delay elements are often used in various types
of high-speed integrated circuits,
mainly intended for delay c... [more]
VLD2013-59 ICD2013-83 IE2013-59
pp.71-76
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