Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, ICD, VLD |
2025-03-05 16:45 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
Analog Primitive Cell Identification for Large-scale Analog Circuit with Graph Neural Network Chen Geng, Shigetoshi Nakatake (Univ. of Kitakyushu), Nobuto Ono, Katsuya Nishioka, Shigeya Yamaguchi, Takahiro Hikida, Noriteru Matsubara, Yukichi Todoroki (Jedat) |
[more] |
|
HWS, ICD, VLD |
2025-03-07 10:35 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
Performance Evaluation of Heart Sound Classification Using CNN, BNN, TNN, and SNN Reo Taniguchi, Haruto Furuta, Yutaro Yamanaka, Shigetoshi Nakatake (Univ. of Kitakyushu) |
[more] |
|
MSS, CAS, SIP, VLD |
2023-07-06 13:00 |
Hokkaido |
(Hokkaido, Online) (Primary: On-site, Secondary: Online) |
[Panel Discussion]
Democratization of Researches in Circuits and Systems fields and Initiatives in Technical Groups Makoto Ikeda (The Univ. of Tokyo), Yasutoshi Aibara (OVT), Shigetoshi Nakatake (The Univ. of Kitakyushu), Takayuki Nakachi (Univ. of Ryukyus), Shingo Yamaguchi (Yamaguchi Univ.) CAS2023-7 VLD2023-7 SIP2023-23 MSS2023-7 |
Open Access initiatives, which allow access and use of research results funded by public research funds not only by the ... [more] |
CAS2023-7 VLD2023-7 SIP2023-23 MSS2023-7 pp.34-36 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2020-02-28 13:00 |
Kagoshima |
Yoron-cho Chuou-Kouminkan (Kagoshima) |
Design and Post-layout Simulation Verification of PLA Reconfigurable Decoder with General-purpose Logic Switch Daiki Ishikawa, Nobuyuki Yahiro, Shigetoshi Nakatake (Univ. of Kitakyusyu) CPSY2019-111 DC2019-117 |
[more] |
CPSY2019-111 DC2019-117 pp.171-176 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2020-02-28 13:20 |
Kagoshima |
Yoron-cho Chuou-Kouminkan (Kagoshima) |
DAC-based Multiplier in Analog-digital Mixed-signal Perceptron Circuit Jinichiro Noguchi, Shigetoshi Nakatake (Univ. of Kitakyushu) CPSY2019-112 DC2019-118 |
[more] |
CPSY2019-112 DC2019-118 pp.177-181 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2019-03-17 13:00 |
Kagoshima |
Nishinoomote City Hall (Tanega-shima) (Kagoshima) |
MOSFET-based ultra high resistance configuration for ultra low current sensing Xinghuai Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) CPSY2018-103 DC2018-85 |
In this work, we propose a method to configure an ultrahigh resistance of 1GΩ or more on a chip, which is used for I-V c... [more] |
CPSY2018-103 DC2018-85 pp.103-108 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2019-03-17 13:40 |
Kagoshima |
Nishinoomote City Hall (Tanega-shima) (Kagoshima) |
On estimation of intravesical urine volume using AC impedance method Ryosuke Sakai, shigetoshi nakatake (Univ. of Kitakyushu) CPSY2018-105 DC2018-87 |
In this work, in order to prevent urinary incontinence caused by various functional diseases, we aim to estimate the uri... [more] |
CPSY2018-105 DC2018-87 pp.115-119 |
VLD, HWS (Joint) |
2018-03-02 09:00 |
Okinawa |
Okinawa Seinen Kaikan (Okinawa) |
On-chip and ultra low current measurement circuit based on potentiostat method Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2017-119 |
We propose a current measurement circuit using on - chip high resistance by MOSFET. Due to advances in biosensing techno... [more] |
VLD2017-119 pp.181-186 |
VLD, CAS, MSS, SIP |
2016-06-17 16:40 |
Aomori |
Hirosaki Shiritsu Kanko-kan (Aomori) |
On Study of Data Reliability of Threshold Sensing with Majority Circuit Akito Hoshide, Bo Liu, Takuro Ishida, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2016-35 VLD2016-41 SIP2016-69 MSS2016-35 |
[more] |
CAS2016-35 VLD2016-41 SIP2016-69 MSS2016-35 pp.191-196 |
VLD, CAS, MSS, SIP |
2016-06-17 17:00 |
Aomori |
Hirosaki Shiritsu Kanko-kan (Aomori) |
Analog Characterization Module based on A/D and D/A Converters Daishi Isogai, Bo Liu, Futa Yoshinaka, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2016-36 VLD2016-42 SIP2016-70 MSS2016-36 |
[more] |
CAS2016-36 VLD2016-42 SIP2016-70 MSS2016-36 pp.197-202 |
VLD, CAS, MSS, SIP |
2016-06-17 17:20 |
Aomori |
Hirosaki Shiritsu Kanko-kan (Aomori) |
Soft-Coupling Module with A/D and D/A Converters Futa Yoshinaka, Bo Liu, Daishi Isogai, Shigetoshi Nakatake (univ.kitakyushu) CAS2016-37 VLD2016-43 SIP2016-71 MSS2016-37 |
[more] |
CAS2016-37 VLD2016-43 SIP2016-71 MSS2016-37 pp.203-208 |
RCC, ASN, RCS, NS, SR (Joint) |
2015-07-31 09:00 |
Nagano |
JA Naganoken Bldg. (Nagano) |
A sensor-based visualizable auscultatory blood pressure measurement learning support tool Chooi-Ling Goh (Design Algorithm Laboratory), Shigetoshi Nakatake (Univ. of Kitakyushu) ASN2015-51 |
In order to help the healthcare practitioners to master the skill of measuring blood pressure by auscultatory method mor... [more] |
ASN2015-51 pp.177-182 |
RECONF |
2015-06-20 14:25 |
Kyoto |
Kyoto University (Kyoto) |
Tile-base PLA Cell with Uni-Switch Structure Atsushi Nanri, Kosuke Murakami, Daijiro Murooka, Takuya Hirata, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) RECONF2015-23 |
[more] |
RECONF2015-23 pp.125-130 |
VLD |
2015-03-02 14:55 |
Okinawa |
Okinawa Seinen Kaikan (Okinawa) |
Symmetrical Routing based on Set-pair Routing and Mixed Integer Programming Masato Ito, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-157 |
This paper proposes a routing algorithm of high routability focusing on symmetrical routing used in analog layout. In a ... [more] |
VLD2014-157 pp.25-30 |
VLD |
2015-03-04 09:15 |
Okinawa |
Okinawa Seinen Kaikan (Okinawa) |
On PLL Layouts Evaluation based on Transistor-array Style Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-175 |
The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that uni... [more] |
VLD2014-175 pp.123-128 |