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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD [detail] 2020-03-06
13:00		 Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)		 Fundamental Study on Fault Analysis with Non-Uniform Faulty Values Caused at Fault Injection into Sequential Circuit
Takumi Okamoto, Daisuke Fujimoto (NAIST), Kazuo Sakiyama, Li Yang (UEC), Yu-ichi Hayashi (NAIST) VLD2019-128 HWS2019-101		 Fault analysis for the cryptographic module is roughly divided into two phases; those are injecting transient faults and... [more] VLD2019-128 HWS2019-101
pp.197-201
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
13:25		 Kanagawa Hiyoshi Campus, Keio University A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87		 Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] VLD2015-105 CPSY2015-137 RECONF2015-87
pp.209-214
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
13:45		 Kagoshima   A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2013-99 DC2013-65		 Due to progressing the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay... [more] VLD2013-99 DC2013-65
pp.275-280
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-26
16:50		 Fukuoka Centennial Hall Kyushu University School of Medicine A Delay Tuning Method of Programmable Delay Element with Two Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (UoA) VLD2012-69 DC2012-35		 Due to progressing the process technology in LSI and increasing delay variations of interconnection and gate delays afte... [more] VLD2012-69 DC2012-35
pp.57-62
VLD 2011-03-03
16:05		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Performance Evaluation of Statistical Static Timing Analysis Using Gaussian Mixture Models
Tomoyuki Fujimori, Shuji Tsukiyama (Chuo Univ), Masahiro Fukui (Ritsumeikan Univ) VLD2010-135		 With the progress of micro-technology, the within die process variability is increasing, and the statistical static timi... [more] VLD2010-135
pp.111-116
CPSY 2005-12-16
14:00		 Tochigi Academia Hall, Utsunomiya Univ. Exploiting Typical Delays to Boost Instruction Collapsing
Toshinori Sato, Akihiro Chiyonobu (KIT) 		The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide des... [more] CPSY2005-36
pp.19-24
 Results 1 - 6 of 6  /   
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