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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| VLD | 2009-03-12 14:15 |
Okinawa | Automatic generation of Network-on-Chip topology under link length and latency constraint Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST) VLD2008-148 |
With wire delay becoming dominant compared to transistor delay in deep-submicron era, the performance of SoC is more aff... [more] | VLD2008-148 pp.129-134 |
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| CS, SIP, CAS | 2008-03-07 09:50 |
Yamaguchi | Yamaguchi University | Improved Method of Multi-Branched Bus Driven Floorplanning Yosuke Taira, Kunihiro Fujiyoshi (TUAT) CAS2007-132 SIP2007-207 CS2007-97 |
sequence-pair, バスドリブン, フロアプラン設計, 増加部分列, 減少部分列 sequence-pair, Bus-driven, floorplanning, increasing subsequence, decre... [more] |
CAS2007-132 SIP2007-207 CS2007-97 pp.41-46 |
| VLD, IPSJ-SLDM | 2007-05-11 14:10 |
Kyoto | Kyodai Kaikan | An algorithm of power grid optimization for high-level floorplan Takayuki Hayashi, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.) |
Recent rapid growth of the narrow and fine patterning technology faces many difficulties of power grid design , e.g. IR ... [more] | VLD2007-15 pp.49-54 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-17 16:00 |
Tokyo | Keio Univ. Hiyoshi Campus | A Parallel Algorithm Based on Genetic Algorithm and Tabu Search for LSI Floorplanning and Its Implementation on a PC Cluster Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) |
This paper proposes a parallel floorplanning algorithm for VLSI floorplanning, which was based on genetic algorithm (GA)... [more] | VLD2006-90 CPSY2006-61 RECONF2006-61 pp.31-36 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-25 16:50 |
Kanagawa | Architecture for Crossover based on Sequence Pair Ryousuke Kanemitsu, Akinori Bito, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan University) |
The floor planning technique that uses GA based on the sequence pair for the solution search is proposed and it obtains ... [more] | VLD2004-109 CPSY2004-75 pp.69-74 |
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