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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, IPSJ-ARC, IPSJ-HPC 2023-12-05
17:40		 Okinawa Okinawa Industry Support Center
(Primary: On-site, Secondary: Online)		 Evaluation of conversion overheads for the sparse matrix format appliying indices of the non-zero elements dictionary compression to accelerate SpMV on GPU
Shun Murakami (JAIST), Kazunori Yoneda, Iwamura Takashi, Masahiro Watanabe (Fujitsu Japan), Yasushi Inoguchi (JAIST) CPSY2023-31		 In recent years, as numerical simulations have become increasingly complex and large-scale. There is a growing demand fo... [more] CPSY2023-31
pp.25-30
CPSY, IPSJ-ARC, IPSJ-HPC 2023-12-06
17:15		 Okinawa Okinawa Industry Support Center
(Primary: On-site, Secondary: Online)		 An Efficient Sparse Matrix Storage Format for Sparse Matrix-Vector Multiplication and Sparse Matrix-Transpose-Vector Multiplication on GPUs
Ryohei Izawa, Yasushi Inoguchi (JAIST) CPSY2023-37		 The utilization of sparse matrix storage formats is widespread across various fields, including scientific computing, ma... [more] CPSY2023-37
pp.58-63
SDM, ICD, ITE-IST [detail] 2021-08-18
09:30		 Online Online [Invited Talk] Analog in-memory computing in FeFET based 1T1R array for low-power edge AI applications
Daisuke Saito, Toshiyuki Kobayashi, Hiroki Koga (SONY), Yusuke Shuto, Jun Okuno, Kenta Konishi (SSS), Masanori Tsukamoto, Kazunobu Ohkuri (SONY), Taku Umebayashi (SSS), Takayuki Ezaki (SONY) SDM2021-36 ICD2021-7		 Deep neural network (DNN) inference for edge AI requires low-power operation, which can be achieved by implementing mass... [more] SDM2021-36 ICD2021-7
pp.33-37
HWS, VLD [detail] 2021-03-03
13:00		 Online Online [Memorial Lecture] Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture
Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. Tokyo) VLD2020-71 HWS2020-46		 There is an obvious trend to make use of hardware including many-core CPU, GPU and FPGA, to conduct computationally inte... [more] VLD2020-71 HWS2020-46
pp.24-29
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