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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIS | 2017-12-15 09:20 |
Tottori | Tottori Prefectural Center for Lifelong Learning | A Proposal about Memory Usage Reduction Method of Non-local Processing Johei Matsuoka (TUT), Takanori Koga (NIT, Tokuyama College), Noriaki Suetake (Yamaguchi Univ.)  SIS2017-46 |
In this report, we describe reduction methods of use memory of non-local processing. Non-local processing is excellent n... [more] | SIS2017-46 pp.75-78 |
| IT, ISEC, WBS | 2016-03-10 13:40 |
Tokyo | The University of Electro-Communications | Collision-Free Rainbow Table Structure Yuki Tabata, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa (NDA) IT2015-114 ISEC2015-73 WBS2015-97 |
Rainbow table is a method to crack the password in high speed from hash values. Collision of password candidates occurs,... [more] | IT2015-114 ISEC2015-73 WBS2015-97 pp.81-88 |
| VLD | 2015-03-03 16:15 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173 |
Non-volatile memory is superior to SRAM in terms of its high density and low leakage power but it consumes larger writ... [more] |
VLD2014-173 p.115 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI, unnecessary parts should be powered off with fine granularity, and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
| NC, MBE (Joint) |
2013-07-19 09:30 |
Tokushima | The University of Tokushima | A neuroscientific explanation for the brain's memory system with the cocktail party effect by the iterative learning method
-- A Hebb's learning model for the network system of neurons with the analog-digital operating characteristics -- Miyuki Seino (Seino Information System) NC2013-15 |
This paper describes the cocktail party effect as a phenomenon of the brain’s active memory system by iterative learning... [more] | NC2013-15 pp.1-6 |
| MSS, CAS, VLD, SIP | 2011-07-01 15:40 |
Okinawa | Okinawa-Ken-Seinen-Kaikan | A Near-Lossless Image Compression Method for Frame Memory Size Reduction Takashi Nakamae (Osaka Univ.), Akihisa Yamada, Masayuki Yamaguchi (Sharp), Takao Onoye (Osaka Univ.) CAS2011-29 VLD2011-36 SIP2011-58 MSS2011-29 |
In recent yeras, a variety of digital processing of high resolution images is performed in digital appliances, such as l... [more] | CAS2011-29 VLD2011-36 SIP2011-58 MSS2011-29 pp.163-168 |
| PRMU | 2009-06-19 13:00 |
Hokkaido | Hokkaido Univ. | Memory Reduction with Bloomier Filters for Specific Object Recognition Katsufumi Inoue, Koichi Kise (Osaka Prefecture Univ.) PRMU2009-56 |
pecific object recognition based on nearest neighbor search of feature vectors required a huge amount of memory to store... [more] | PRMU2009-56 pp.101-106 |
| CAS | 2008-02-01 11:20 |
Okinawa | An Image Compression Method for Frame Memory Reduction Hiroshi Kato (Osaka Univ.), Akihisa Yamada (SHARP), Takao Onoye (Osaka Univ.) CAS2007-99 |
In recent, in large-sized plasma or LCD TV sets, a variety of digital processing of high resolution images are performed... [more] | CAS2007-99 pp.31-36 |
|
| CPM, ICD | 2008-01-18 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg | [Tutorial Lecture]
Survey of Analysis Techniques for On-chip Power Distribution Networks Takashi Sato (Tokyo Tech.) CPM2007-140 ICD2007-151 |
Primary techniques and recent trends in power distribution network (PDN) analysis are reviewed in this paper. Quality ... [more] |
CPM2007-140 ICD2007-151 pp.71-76 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
This paper formulates a code placement problem to optimize the total energy consumption of a CPU core, on-chip memories ... [more] | VLD2007-75 DC2007-30 pp.31-36 |
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