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Committee Date Time Place Paper Title / Authors Abstract Paper #
SCE 2020-01-17
13:15		 Kanagawa   [Poster Presentation] Design and Evaluation of a 32-word by 8-bit Register File Using Adiabatic Quantum Flux Parametron Logic
Tomohiro Tamura, Naoki Takeuchi, Christopher Ayala, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2019-50		 Extremely energy-efficient logic devices are required for future energy-efficient highperformance computing systems. Sup... [more] SCE2019-50
pp.83-86
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-11
13:40		 Hokkaido Hokkaido University Write Reduction of Internal Registers for Non-volatile RISC Processors
Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40		 Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because ... [more] CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40
pp.213-218
SDM, ICD 2013-08-02
14:25		 Ishikawa Kanazawa University [Invited Talk] A 10th Generation 16-Core SPARC64 Processor for Mission-Critical UNIX Server
Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi (Fujitsu), Yoichi Koyanagi (Fujitsu Laboratories), Ryuji Iwatsuki, Kazumi Hayasaka (Fujitsu), Taiki Uemura (Fujitsu Semiconductor), Gaku Itou, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada (Fujitsu) SDM2013-83 ICD2013-65		 A 10th generation SPARC64 processor is fabricated in enhanced 28nm CMOS process. It runs at 3.0GHz and contains 16 cores... [more] SDM2013-83 ICD2013-65
pp.95-98
ICD, IPSJ-ARC 2008-05-13
10:00		 Tokyo   Evaluation of Area-Oriented Register Cache
Ryota Shioya (Univ. Tokyo), Hidetsugu Irie (JST), Masahiro Goshima, Shuichi Sakai (Univ. Tokyo) 		Register file is one of the most costly units in recent superscalar processor. In this paper, we evaluate Area-oriented ... [more] ICD2008-19
pp.13-18
ICD, IPSJ-ARC 2006-06-08
14:30		 Kanagawa   Physical Register Access Analysis for Temperature-Aware Microarchitecture
Toshinori Sato (Kyushu Univ.), Yuji Kunitake, Akihiro Chiyonobu (Kyushu Inst. Tech.) 		While the improvements in clock frequency and transistor density have achieved the continuous increase in microprocessor... [more] ICD2006-46
pp.37-42
IE, SIP, ICD, IPSJ-SLDM 2004-10-21
15:25		 Yamagata   Noise and process variation-tolerant multi-ported register file using 130 nm technology
Yuuichirou Ikeda, Masaya Sumita (Matsushita Electric Industrial) 		We have developed a 32-bit, 64-word 9-read, 7-write ported register file for a processor based on 130 nm process technol... [more] SIP2004-87 ICD2004-119 IE2004-63
pp.67-72
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