Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
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SDM2005-143
A -90dBc@10kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit
Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa (Matsushita Electric Industrial Co., Ltd)
pp. 1 - 6
SDM2005-144
A Low-IF CMOS Single-Chip Bluetooth EDR Transmitter with Digital I/Q Mismatch Trimming Circuit
Hiroki Ishikuro, Daisuke Miyashita, Taro Shimada, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada, Fumitoshi Hatori (Toshiba)
pp. 7 - 12
SDM2005-145
A 106dB audio digital-to-analog converter employing segment flipping technology combined with cascaded dynamic element matching
Toru Ido, Sonny Ishizuka (TIJ)
pp. 13 - 18
SDM2005-146
[Special Invited Talk]
HfSiON
-- its high applicability as the alternative gate dielectric based on the high thermal stability and the remaining issue --
Akira Nishiyama, Masato Koyama, Yuuichi Kamimuta, Masahiro Koike, Ryosuke Iijima, Takeshi Yamaguchi, Masamichi Suzuki, Tsunehiro Ino, Mizuki Ono (Toshiba)
pp. 19 - 24
SDM2005-147
HfSiON Gate Dielectrics Design for Mixed Signal CMOS
Kenji Kojima, Ryosuke Iijima, Tatsuya Ohguro, Takeshi Watanabe, Mariko Takayanagi, Hisayo S. Momose, Kazunari Ishimaru, Hidemi Ishiuchi (TOSHIBA)
pp. 25 - 30
SDM2005-148
Improvement of threshold voltage asymmetry by Al compositional mudulation and partially silicided gate electrode for Hf-based high-k CMOSFETs
Masaru Kadoshima, Arito Ogawa, Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Nobuyuki Mise, Kunihiko Iwamoto (MIRAI-ASET), Shinji Migita (MIRAI-ASRC, AIST), Hideaki Fujiwara, Hideki Satake, Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, The Univ. of Tokyo)
pp. 31 - 36
SDM2005-149
Gate work-function modulation in SiON/poly-Si gate stacks, and its impact on low power devices
-- Advantage of sub-monolayer Hf at SiON/poly-Si interface --
Jiro Yugami (Renesas), Yasuhiro Shimamoto (Hitachi), Masao Inoue, Masaharu Mizutani, Takashi Hayashi, Katsuya Shiga, Fumiko Fujita, Jyunichi Tuchimoto, Yoshikazu Ohno, Masahiro Yoneda (Renesas)
pp. 37 - 42
SDM2005-150
A Novel Voltage Sensing 1T/2MTJ Cell with Resistance Ratio for Highly Stable and Scalable MRAM
Masaki Aoki, Hiroshi Iwasa, Yoshihiro Sato (Fujitsu Lab)
pp. 43 - 48
SDM2005-151
0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process
Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi (STARC)
pp. 49 - 54
SDM2005-152
A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi)
pp. 55 - 60
SDM2005-153
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories
Kazuo Otsuga, Hideaki Kurata (Hitachi, Ltd.), Kenji Kozakai, Satoshi Noda (Renesas), Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi (Hitachi, Ltd.)
pp. 61 - 66
SDM2005-154
Robust Device Design in FinFET SRAM for hp22nm Technology Node
Kimitoshi Okano, Tatsuya Ishida, Takahiko Sasaki, Takashi Izumida, Masaki Kondo, Makoto Fujiwara, Nobutoshi Aoki, Satoshi Inaba, Nobuaki Otsuka, Kazunari Ishimaru, Hidemi Ishiuchi (Toshiba)
pp. 67 - 72
SDM2005-155
High-k; Last Card for the Leakage Currents
Tadayoshi Enomoto (Chuo Univ.), Mariko Takayanagi (Toshiba), Shigeo Satoh (Fujitu), Koji Nii (Renesas), Akira Nishiyama (Toshiba), ハセ タカシ (NEC), Mototsugu Hamada (Toshiba), Jiro Yugami (Renesas)
pp. 73 - 78