IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2008-05-09 / Issue Date : 2008-05-02

VLD2008-7
[Invited Talk] NoizeProblems in LSI Design:Challenges and Approaches
Makoto Nagata (Kobe Univ.)
pp. 1 - 6

VLD2008-8
Fast Wire Length Estimation in Obstructive Block Placement
Shuting Li (Univ. of Kitakyushu), Tan Yan (Univ. of Illinois at Urbana-Champaign), Yasuhiro Takashima, Hiroshi Murata (Univ. of Kitakyushu)
pp. 7 - 12

VLD2008-9
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
pp. 13 - 18

VLD2008-10
Fine-Grained Power Gating Based on the Controlling Value of Logic Gates
Lei Chen (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.)
pp. 19 - 24

VLD2008-11
A Sub 100 mW H.264/AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding
Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
pp. 25 - 30

VLD2008-12
A Dependable SRAM with high-reliability mode and high-speed mode.
Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
pp. 31 - 36

VLD2008-13
On Synthesizing a Heterogeneous Multiprocessor System under Real-Time and SEU Vulnerability Constraints
Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST)
pp. 37 - 42

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan