IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 108, Number 22

VLSI Design Technologies

[PREV] [NEXT]

[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]

[PROGRAM] [BULK PDF DOWNLOAD]

Table of contents

VLD2008-1
[Invited Talk] HW/SW Co-verification Method Using FPGAs
Yuichi Nakamura, Kouhei Hosokawa (NEC)
pp. 1 - 6

VLD2008-2
Checker Circuit Generation for System Verilog Assertions in Prototyping Verification
Mengru Wang, Shinji Kimura (Waseda Univ.)
pp. 7 - 12

VLD2008-3
Checker Generation of Assertions with Local Variables for Model Checking
Sho Takeuchi, Kiyoharu Hamaguchi, Yosuke Kakiuchi, Toshinobu Kashiwabara (Osaka Univ.)
pp. 13 - 18

VLD2008-4
Improvement Technique of Binding for Multiplexer Reduction
Sho Kodama, Yusuke Matsunaga (Kyushu Univ.)
pp. 19 - 24

VLD2008-5
Radix-2 Butterfly Circuit Architecture Using Selector Logic
Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print)
pp. 25 - 30

VLD2008-6
Improvement of swtching activity aware algorithm for prefix graph synthesis
Taeko Matsunaga, Shinji Kimura (Waseda Univ), Yusuke Matsunaga (Kyushu Univ)
pp. 31 - 36

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.