IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2008-11-18 / Issue Date : 2008-11-11

CPSY2008-37
A Path-Based Thread Partitioning Technique Considering Loop Structures
Hirohito Ogawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)
pp. 1 - 6

CPSY2008-38
Program Behavior Analysis Based on Loop Paths
Hideto Yanome, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)
pp. 7 - 12

CPSY2008-39
Initial Examination of Detour Routing that uses Global Information
Hiroki Mori, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.)
pp. 13 - 18

CPSY2008-40
Decoded Instruction Cache for Server Virtualization Feature
Toshiomi Moriki, Naoya Hattori, Yuji Tsushima, Eiichiro Oiwa (Hitachi, Ltd., Central Research Laboratory)
pp. 19 - 24

CPSY2008-41
Memory Virtualization Mechanism for Server Virtualization
Naoya Hattori, Toshiomi Moriki, Yuji Tsushima, Norimitsu Hayakawa (Hitachi, ltd)
pp. 25 - 30

CPSY2008-42
An optimization method for MIMD controlled data communication of MX Core
Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 31 - 36

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan