Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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DC2010-8
A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST)
pp. 1 - 6
DC2010-9
A Class of Partial Thru Testable Sequential Circuits with Multiplexers
Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 7 - 11
DC2010-10
A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths
Yuki Yoshikawa, Shun Maruya, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 13 - 18
DC2010-11
A test pattern matching method on BAST architecture using don't care identification for the detection of random pattern resistant faults
Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
pp. 19 - 24
DC2010-12
Note on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 25 - 30
DC2010-13
An I/O Sequence Slicing Method for Post-silicon Debugging
Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo.)
pp. 31 - 36
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.