Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2010-18
Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration
Hiroyuki Kawai, Moritoshi Yasunaga (Tsukuba Univ.)
pp. 1 - 6
RECONF2010-19
Real-time detection of line segments on FPGA
Jianyun Zhu, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 7 - 12
RECONF2010-20
A Regular Expression Matching Circuit Based on an NFA with Multi-Character Consuming
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT)
pp. 13 - 18
RECONF2010-21
Finite Field Arithmetic on a Reconfigurable Processor with Variable Word Size
Yuichiro Shibata, Ryuichi Harasawa, Kiyoshi Oguri (Nagasaki Univ.)
pp. 19 - 24
RECONF2010-22
A Consideration of Reconfigurable Processor for RSA Cryptography
Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (hcu)
pp. 25 - 30
RECONF2010-23
Accelerating HMMER search using FPGA Grid
Toyokazu Takagi, Tsutomu Maruyama (Tsukuba Univ.)
pp. 31 - 36
RECONF2010-24
Hardware Lossless-Compressors of Floating-Point Data Streams to Enhance Memory Bandwidth
Kentaro Sano, Kazuya Katahira, Satoru Yamamoto (Tohoku Univ.)
pp. 37 - 42
RECONF2010-25
Evaluation of Multiple-Precision Floating-Point Accelerator HP-DSFP through Applications.
Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
pp. 43 - 48
RECONF2010-26
An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN)
pp. 49 - 54
RECONF2010-27
Design and Implementation of a Layout Tool for the MPLD Architecture
Ken Taomoto, Hideyuki Kawabata, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura (Hiroshima City Univ.)
pp. 55 - 60
RECONF2010-28
A Peformance Estimation Method for Dynamically Reconfigurable Architecture in Stream Processing
Fumihiko Hyuga, Takashi Yoshikawa (Toshiba)
pp. 61 - 66
RECONF2010-29
[Invited Talk]
Applications of optically reconfigurable gate arrays
Minoru Watanabe (Shizuoka Univ.)
pp. 67 - 71
RECONF2010-30
A MEMS addressing technique in optically reconfigurable gate arrays
Hironobu Morita, Minoru Watanabe (Shizuoka Univ.)
pp. 73 - 77
RECONF2010-31
COGRE: A Novel Compact Logic Cell Architecture for Area Reduction
Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 79 - 84
RECONF2010-32
An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device
Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 85 - 90
RECONF2010-33
Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 91 - 95
RECONF2010-34
Removing context memory from Multi-context Dynamically Reconfigurable Processors
Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.)
pp. 97 - 102
RECONF2010-35
Power reduction for Dynamically Reconfigurable Processor Array with reducing the number of reconfiguration
Masayuki Kimura, Kazuei Hironaka, Hideharu Amano (Keio Univ.)
pp. 103 - 108
RECONF2010-36
Performance Evaluation of the SIMD/MIMD Dynamic Mode Switching Processor IMAPCAR2
Shorin Kyo, Shohei Nomoto, Shinichiro Okazaki (RE)
pp. 109 - 114
RECONF2010-37
Quantitative Performance Evaluation of Arbiter PUFs on FPGAs
Yohei Hori (AIST), Takahiro Yoshida (Chuo Univ.), Toshihiro Katashita, Akashi Satoh (AIST)
pp. 115 - 120
RECONF2010-38
Implementation and Evaluation of ScalableCore System 2.0
Yoshito Sakaguchi, Shinya Takamaeda, Kenji Kise (Tokyo Tech)
pp. 121 - 126
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.