IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Dependable Computing

Workshop Date : 2011-06-24 / Issue Date : 2011-06-17

DC2011-8
An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults
Satoshi Fukumoto, Masayuki Arai, Shinya Hara, Kazuhiko Iwasaki (TMU)
pp. 1 - 4

DC2011-9
Effective multi-cycle signatures in testable response analyzers
Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 5 - 10

DC2011-10
A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyuushu Univ)
pp. 11 - 16

DC2011-11
[Invited Talk] International Conference Report - VTS2011(29th IEEE VLSI Test Symposium)
Kazumi Hatayama (NAIST)
pp. 17 - 22

DC2011-12
A don't care identification method with care bit distribution control -- Application to capture power reduction --
Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ)
pp. 23 - 28

DC2011-13
Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification
Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm)
pp. 29 - 34

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan