IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Signal Processing

Workshop Date : 2011-10-24 - 2011-10-25 / Issue Date : 2011-10-17

SIP2011-62
[Invited Talk] Toward Machine Vision Technology Overcoming the Pixel Resolution Limit -- From 3D Vision to Biometrics Authentication --
Takafumi Aoki (Tohoku Univ.)
pp. 1 - 6

SIP2011-63
Three-Dimensional Accelerator Architecture for Image Recognition
Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
pp. 7 - 12

SIP2011-64
Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer
Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.)
pp. 13 - 18

SIP2011-65
An H.264/AVC video encoder LSI for broadcasting infrastructure and its applications
Koyo Nitta, Mitsuo Ikeda (NTT), Hiroe Iwasaki (NEL), Kazuto Kamikura, Hirohisa Jozawa (NTT)
pp. 19 - 24

SIP2011-66
An H.264 Full HD 60i Double Speed Encoder IP Supporting Both MBAFF and Field-Pic Structure
Akira Moriya, Hajime Matsui, Takaya Ogawa, Atsushi Mochizuki, Kazuyo Kanou, Hiromitsu Nakayama, Sho Kodama, Shinichiro Koto, Shunichi Ishiwata (Toshiba)
pp. 25 - 30

SIP2011-67
High efficiency VLSI architecture for H.264 CABAC decoder by using residual data accelalator
Gen Fujita (Osaka Electro-comm. Univ.), Kenji Watanabe (Synthesis Corp.), Toru Homemoto, Ryoji Hashimoto (Osaka Univ.)
pp. 31 - 35

SIP2011-68
Improvement of 3D Shape Reconstruction by Position Estimation of Occluding Contours
Akio Ishikawa, Hiroshi Sankoh, Sei Naito (KDDI R&D Labs.)
pp. 37 - 42

SIP2011-69
Near Infrared Reflected Intensity Based Material Recognition and Its Application
Muhammad Attamimi, Tomoaki Nakamura, Takayuki Nagai (UEC Tokyo)
pp. 43 - 48

SIP2011-70
A method for accurate estimation of venous shapes from small picture signals.
Koji Kashihara, Keisuke Takahashi, Momoyo Ito, Minoru Fukumi (Tokushima Univ.)
pp. 49 - 54

SIP2011-71
A Study on Biometrics Authentication Method Using Features in Utterance
Atsushi Sayo, Yoshinobu Kajikawa, Mitsuji Muneyasu (Kansai Univ.)
pp. 55 - 60

SIP2011-72
[Invited Talk] Heterogeneous Many-Core Application Processor Architecture for Ultra-High-Quality Image Reproduction
Yukoh Matsumoto (TOPS)
pp. 67 - 71

SIP2011-73
FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 73 - 76

SIP2011-74
Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors
Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 77 - 82

SIP2011-75
Dynamically reconfigurable vision-chip architecture using a lens array
Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito (Shizuoka Univ.)
pp. 83 - 87

SIP2011-76
Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption
Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.)
pp. 89 - 94

SIP2011-77
Simultaneous Optimization of a CDFG Structure and a Schedule Based on Super-node Representation
Akira Hirata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 101 - 105

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan