IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 111, Number 435

Dependable Computing

Workshop Date : 2012-02-13 / Issue Date : 2012-02-06

[PREV] [NEXT]

[TOP] | [2008] | [2009] | [2010] | [2011] | [2012] | [2013] | [2014] | [Japanese] / [English]

[PROGRAM] [BULK PDF DOWNLOAD]


Table of contents

DC2011-76
Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection
Yoshihiro Ohkawa, Yukiya Miura (TMU)
pp. 1 - 6

DC2011-77
An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits
Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
pp. 7 - 12

DC2011-78
Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test
Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech)
pp. 13 - 18

DC2011-79
Note on Layout-Aware High Accuracy Estimation of Fault Coverage
Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 19 - 24

DC2011-80
A method to reduce shift-toggle rate for low power BIST
Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT)
pp. 25 - 29

DC2011-81
A new problem at Boundary-Scan testing -- an internal disruption within IC during interconnect testing --
Shuichi Kameyama (Fujitsu & Ehime Univ.), Masayuki Baba (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
pp. 31 - 35

DC2011-82
A method to reduce the number of test patterns for transition faults using control point insertions
Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ)
pp. 37 - 42

DC2011-83
A Test Generation Method for Synchronously Designed QDI Circuits
Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST)
pp. 43 - 48

DC2011-84
An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation
Michihiro Shintani, Takashi Sato (Kyoto Univ.)
pp. 49 - 54

DC2011-85
Dynamic Test Scheduling for In-Field Aging Detection
Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST)
pp. 55 - 60

DC2011-86
Evaluation of a thermal and voltage estimation circuit for field test
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU)
pp. 61 - 66

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan