IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 111, Number 461

Computer Systems

Workshop Date : 2012-03-02 - 2012-03-03 / Issue Date : 2012-02-24

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Table of contents

CPSY2011-83
Profiling-based Source to Source Compiler for GPGPU
Atsushi Yumoto, Nobuhiko Sugino (Titech)
pp. 79 - 84

CPSY2011-84
Design and implementation of distributed TLB mechanism for heterogeneous multi-core processors
Daiki Kawase, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
pp. 85 - 90

CPSY2011-85
Design and implementation of I/O control mechanism for heterogeneous multi-core processors
Yuki Kawaguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
pp. 91 - 96

CPSY2011-86
Multi Core Task Mapping Method by Weight Control for Dependencies between Descendent Tasks
Noriaki Suzuki, Takahiro Kumura, Yuichi Nakamura (NEC)
pp. 97 - 102

CPSY2011-87
An Implementation and Evaluation of MapReduce Framework with Thread Virtualization Environment for Cell Broadband Engine Clusters
Masahiro Yamada, Tetsuya Nakahama (Keio Univ.), Masato Yoshimi (Doshisha Univ.), Hideharu Amano (Keio Univ.)
pp. 169 - 174

CPSY2011-88
An Implementation and Evaluation of Automatic MPI Expansion tool for Cell/B.E. cluster
Tetsuya Nakahama, Masahiro Yamada (Keio Univ.), Masato Yoshimi (Doshisya Univ.), Hideharu Amano (Keio Univ.)
pp. 175 - 180

CPSY2011-89
Implementation of Embedded Java VM for Multithreaded Processor
Yasuhito Ito, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
pp. 181 - 186

CPSY2011-90
An Automatic Parallelization Scheme Used in JIT Compilation for Dynamic Language Applications
Ryotaro Ikeda, Nobuhiko Sugino (Tokyo Tech)
pp. 187 - 192

CPSY2011-91
Development of a FPGA based performance evaluation system for a Ultra-Android prototype
Kenji Toda, Osamu Morikawa (AIST), Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Yasumori Hibi, Yukoh Matsumoto (Tops Systems)
pp. 193 - 198

CPSY2011-92
A Case Study of Supervisor Processor for Dependable System
Makoto Fujino, Yoshihiro Ichinomiya, Hiroki Tanaka, Sayaka Yoshiura, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 199 - 204

CPSY2011-93
Time Division Method of Detecting Fault of RAM by Software
Ryoya Ichioka (Mitsubishi Electric)
pp. 205 - 209

CPSY2011-94
Structure Search of Cascaded TMR for Pipelined Processors Based on Genetic Algorithm
Masayuki Arai, Hajime Ide, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 211 - 217

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan