IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2012-11-26 - 2012-11-27 / Issue Date : 2012-11-19

CPSY2012-47
Proposal of Speculative Memory Access Mechanism Based on Snoop Cache
Yuji Sekiguchi, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)
pp. 1 - 6

CPSY2012-48
A Study of Path Prediction Mechanism for Improving Accuracy by using Detailed History Information
Hiroyoshi Jutori, Takanobu Baba, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
pp. 7 - 12

CPSY2012-49
[Invited Talk] Way Selection Cache for Low Power Computing
Koji Inoue (Kyushu Univ.)
p. 13

CPSY2012-50
A Routing Strategy for 3-D NoCs Incorporating Bus and Network
Takahiro Kagami, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 15 - 20

CPSY2012-51
Rethinking virtual channel usage in network-on-chip
Ryosuke Sasakawa, Naoki Fujieda, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech)
pp. 21 - 26

CPSY2012-52
Network Performance of Multifunction On-chip Router Architectures
Shinya Takamaeda-Yamazaki, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.)
pp. 27 - 32

CPSY2012-53
A study on Hardware Trojan embedded Manchurian and its detection approach for triple DES processing
Youhei Mochizuki, Takeshi Kumaki (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ)
pp. 33 - 38

CPSY2012-54
An FPGA Implementation of Reconfigurable Real-Time Vision Architecture
Jorge Hiraiwa, Hideharu Amano (Keio Univ.)
pp. 39 - 44

CPSY2012-55
[Keynote Address] Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects
Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics)
p. 45

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan