Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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DC2012-80
A Hardware Implementation of a SAT Solver for Test Generation with Solution Reuse
Toshiya Mukai, Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 1 - 6
DC2012-81
Accelerating techniques for SAT-based test pattern generation
Yusuke Matsunaga (Kyushu Univ.)
pp. 7 - 12
DC2012-82
Note on Fault Coverage Estimation Using Critical Area Analysis
Yoshihiro Shimizu, Yuta Nakayama, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 13 - 18
DC2012-83
A don't care filling method to improve defect detection capability using stuck-at fault test sets and transition fault test sets
Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ)
pp. 19 - 24
DC2012-84
Characteristic Analysis of Signal Delay for Resistive Open Fault Detection
Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
pp. 25 - 30
DC2012-85
On Fault detection method considering adjacent TSVs for a delay fault in TSV
Masanori Nakamura, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ.of Tokushima)
pp. 31 - 36
DC2012-86
An evaluation of Trojan Circuits on AES Encryption Circuits
Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
pp. 37 - 42
DC2012-87
An Evaluatoin Method of Test Compactors for Secure
Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.)
pp. 43 - 47
DC2012-88
A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application
Shingo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 49 - 54
DC2012-89
Temperature and voltage estimation considering manufacturing variability for a monitoring circuit
Yousuke Miyake, Wataru Tsumori, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 55 - 60
DC2012-90
Data volume reduction method for unknown value handling in built-in self test used in field
Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST)
pp. 61 - 66
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.