IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 113, Number 296

Silicon Device and Materials

Workshop Date : 2013-11-14 - 2013-11-15 / Issue Date : 2013-11-07

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Table of contents

SDM2013-99
[Invited Talk] 2013 SISPAD Review -- transport and reliability --
Nobuya Mori (Osaka Univ.)
pp. 1 - 4

SDM2013-100
[Invited Talk] 2013 SISPAD Review -- Workshop 1 --
Masashi Uematsu (Keio Univ.)
pp. 5 - 8

SDM2013-101
[Invited Talk] Role of Computational Sciences in Design of Modern Electron Devices
Kenji Shiraishi (Nagoya Univ.)
pp. 9 - 14

SDM2013-102
Atomistic Study of Sulfur Diffusion and S2 Formation in Silicon during Low-temperature Rapid Thermal Annealing
Takahisa Kanemura, Koichi Kato, Hiroyoshi Tanimoto, Nobutoshi Aoki, Yoshiaki Toyoshima (Toshiba)
pp. 15 - 20

SDM2013-103
The effect of incorporated elements in nitrogen vacancies on electron trap level in silicon nitride
Kenichiro Sonoda, Eiji Tsukuda, Motoaki Tanizawa, Kiyoshi Ishikawa, Yasuo Yamaguchi (Renesas Electronics)
pp. 21 - 26

SDM2013-104
[Invited Talk] Analysis of Low-Frequency Noise in Silicon Tri-Gate Nanowire Transistors
Masumi Saitoh, Kensuke Ota, Chika Tanaka, Toshinori Numata (Toshiba)
pp. 27 - 30

SDM2013-105
[Invited Talk] Advanced MOSFET simulations using a quantum energy trasport model
Shohiro Sho, Shinji Odanaka (Osaka Univ.)
pp. 31 - 36

SDM2013-106
Analytical drain current and threshold voltage model and device design of short-channel Si nanowire transistors
Chika Tanaka, Daisuke Hagishima (Toshiba), Ken Uchida (Keio Univ.), Toshinori Numata (Toshiba)
pp. 37 - 42

SDM2013-107
Analytic Compact Model of Ballistic and Quasi-ballistic Cylindrical Gate-All-Around MOSFET Incorporating Drain-Induced Barrier Lowering Effect
He Cheng (Nagoya Univ.), Shigeyasu Uno (Ritsumeikan Univ.), Kazuo Nakazato (Nagoya Univ.)
pp. 43 - 48

SDM2013-108
Physical Model and Simulations on Resistive Transition of Pt/TiO2/Pt Capacitor
Yasuhisa Omura, Yusuke Kondo (Kansai Univ.)
pp. 49 - 54

SDM2013-109
Theoretical Modeling of Double-Gate Lateral Tunnel FET
Yasuhisa Omura, Daiki Sato, Shingo Sato (Kansai Univ.), Abhijit Mallik (Univ. of Calcuitta)
pp. 55 - 60

SDM2013-110
NEGF Simulation for Studying Effect of Screening and Impurity Scattering in Junctionless Transistors
Akiko Ueda (Univ. of Tsukuba), Mathieu Luisier (ETH Zurich), Katsuhisa Yoshida, Syuta Honda, Nobuyuki Sano (Univ. of Tsukuba)
pp. 61 - 64

SDM2013-111
Quantum transport simulation of ultrasmall III-V MOSFETs using Wigner Monte Carlo approach
Masaki Ohmori, Shunsuke Koba, Yosuke Maegawa (Kobe Univ.), Hideaki Tsuchiya (Kobe Univ./JST), Yoshinari Kamakura, Nobuya Mori (Osaka Univ./JST), Matsuto Ogawa (Kobe Univ.)
pp. 65 - 70

SDM2013-112
Analysis of Thermoelectric Performance in Silicon Nanostructures Based on Monte Carlo Method
Indra Nur Adisusilo, Kentaro Kukita (Osaka Univ.), Yoshinari Kamakura (Osaka Univ./JST CREST)
pp. 71 - 76

SDM2013-113
Possible Unified Model for the Hooge Parameter in Inversion-Layer-Channel MOSFET
Yasuhisa Omura (Kansai Univ.)
pp. 77 - 82

SDM2013-114
Impacts of Channel Doping on Random Telegraph Signal Noise and Successful Noise Suppression by Mobility Enhancement
Jiezhi Chen, Yusuke Higashi, Izumi Hirano, Yuichiro Mitani (Toshiba)
pp. 83 - 86

SDM2013-115
Reconsideration of Effective MOSFET Channel Length
Kazuo Terada, Kazuhiko Sanai, Katsuhiro Tsuji (Hiroshima City Univ.)
pp. 87 - 91

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan