Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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CPSY2013-58
[Invited Talk]
Circuit design for 3D-stacking using TSV interconnects
Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi)
pp. 1 - 4
CPSY2013-59
[Invited Talk]
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators
Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.)
pp. 5 - 8
CPSY2013-60
[Invited Talk]
Cu Wiring Technology for 3D/2.5D Packaging
Motoaki Tani, Yoshihiro Nakata, Tsuyoshi Kanki, Tomoji Nakamura (Fujitsu Lab.)
pp. 9 - 14
CPSY2013-61
[Invited Talk]
Chip Thinning Technologies for Chip Stacking Packages
Shinya Takyu, Tetsuya Kurosawa (Toshiba)
pp. 15 - 20
CPSY2013-62
[Keynote Address]
The age of Space Discovery Opened by World's First Solar Sail "IKAROS"
Osamu Mori (JAXA)
pp. 21 - 25
CPSY2013-63
[Invited Talk]
Toward VLSI Reliability Enhancement by Reconfigurable Architecture
Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.)
p. 27
CPSY2013-64
Study of the Hardware Trojan for Embedded Processor
Yasushi Tsukada, Shuhei Itaya, Takeshi Kumaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ.)
pp. 29 - 34
CPSY2013-65
Implementation of a fast runtime visualization of a GPU-based electromagnetic simulation using a 3D-FDTD method
Kota Aoki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto (Nagasaki Univ.)
pp. 35 - 40
CPSY2013-66
TinyCSE: Tiny Computer System for Education
Ryosuke Nakamura, Koji Nakano, Yasuaki Ito (Hiroshima Univ.)
pp. 41 - 45
CPSY2013-67
A Study on an optimal architecture for stream mining applications with FPGA
Sayaka Akioka (Meiji Univ.)
pp. 47 - 52
CPSY2013-68
A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing
Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.)
pp. 53 - 58
CPSY2013-69
A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs
Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, Yasuaki Ito (Hiroshima Univ.)
pp. 59 - 64
CPSY2013-70
A study of multi-port shared cache architecture for a multi-core processor on an FPGA
Hongkun Jin, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)
pp. 65 - 70
CPSY2013-71
NoC routers using the marching memory through type
Ryota Yasudo, Takahiro Kagami, Hideharu Amano (Keio Univ.), Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu (Renesas), Tadao Nakamura (Keio Univ.)
pp. 71 - 76
CPSY2013-72
A 3-D NoC architecture using CSMA/CD bus for inter-chip wireless communication
Takahiro Kagami, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 77 - 82
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.