IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 113, Number 325

Reconfigurable Systems

Workshop Date : 2013-11-27 - 2013-11-28 / Issue Date : 2013-11-20

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Table of contents

RECONF2013-39
A High-Speed FFT for a Solar Radio Burst Obvervation on a Radio Telescope
Hiroki Nakahara, Youhei Chishiki (Kagoshima Univ.), Kazumasa Iwai (NAOJ), Hiroyuki Nakanishi (Kagoshima Univ.)
pp. 1 - 6

RECONF2013-40
An Update Method for a CAM Emulator using a LUT Cascade Based on an EVBDD
Kensuke Kushiyama, Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.)
pp. 7 - 12

RECONF2013-41
[Invited Talk] Circuit design for 3D-stacking using TSV interconnects
Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi)
pp. 13 - 16

RECONF2013-42
[Invited Talk] 3D Clock Distribution Using Vertically/Horizontally Coupled Resonators
Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.)
pp. 17 - 20

RECONF2013-43
[Invited Talk] Cu Wiring Technology for 3D/2.5D Packaging
Motoaki Tani, Yoshihiro Nakata, Tsuyoshi Kanki, Tomoji Nakamura (Fujitsu Lab.)
pp. 21 - 26

RECONF2013-44
[Invited Talk] Chip Thinning Technologies for Chip Stacking Packages
Shinya Takyu, Tetsuya Kurosawa (Toshiba)
pp. 27 - 32

RECONF2013-45
[Keynote Address] The age of Space Discovery Opened by World's First Solar Sail "IKAROS"
Osamu Mori (JAXA)
pp. 33 - 37

RECONF2013-46
Soft-core microprocessor for small reconfigurable device
Yuichi Watanabe, Taisuke Yamamoto, Yuki Yoshida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 39 - 44

RECONF2013-47
Mapping of Java bytecode to virtual CGRA with implementation in FPGA
Yuki Ogawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 45 - 50

RECONF2013-48
A trade-off between hardware resources and detection accuracy for FPGA implementation of separability filters
Jimpei Hamamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 51 - 56

RECONF2013-49
ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length
Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 57 - 62

RECONF2013-50
Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems
Yukihito Ishida, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.)
pp. 63 - 68

RECONF2013-51
[Invited Talk] Toward VLSI Reliability Enhancement by Reconfigurable Architecture
Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.)
p. 69

RECONF2013-52
Real Chip evaluation of a low power reconfigurable accelerator with SOTB Technology
Hongliang Su, Hideharu Amano (Keio Univ.)
pp. 71 - 76

RECONF2013-53
Evaluation of The First Flex Power FPGA chip with SOTB transistors
Chao Ma (AIST/Meiji Univ.), Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa (AIST), Toshiyuki Tsutsumi (AIST/Meiji Univ.), Hanpei Koike (AIST)
pp. 77 - 82

RECONF2013-54
Dependability-increasing demonstration of an optically differential reconfigurable gate array
Masato Seo, Minoru Watanabe (Shizuoka Univ.)
pp. 83 - 86

RECONF2013-55
Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD
Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN)
pp. 87 - 92

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan