IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2014-11-26 - 2014-11-28 / Issue Date : 2014-11-19

CPSY2014-72
Development and Evaluation of Pipelining of Heap-Sort Execution for Low-Latency Stream Data Processing
Yoshifumi Fujikawa, Tetsuro Hommura, Tadayuki Matsumura (Hitachi)
pp. 1 - 6

CPSY2014-73
A Large Graph Segmentation Method for Triangle Counting
Tatsuhiro Hirano, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST)
pp. 7 - 12

CPSY2014-74
Parallelization of Shortest Path Search on Various Platforms and Its Evaluation
Shuto Kurebayashi, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST)
pp. 13 - 18

CPSY2014-75
An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders
Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.)
pp. 19 - 23

CPSY2014-76
A complex multiplier using two floating-point fused multiply-add unit
Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.)
pp. 25 - 29

CPSY2014-77
[Invited Talk] Magnetic Resonance (MR) Safety of Implantable Medical Device: Current Status and Future Prospect
Kagayaki Kuroda (Tokai Univ.)
pp. 31 - 34

CPSY2014-78
[Invited Talk] Latest Development and Future Prospect of Mobile Display Technology
Yoshiharu Nakajima (JDI)
pp. 35 - 38

CPSY2014-79
Scalable and Low Latency Structure for Castle of Chips
Hiroshi Nakahara, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 39 - 44

CPSY2014-80
A Distributed Router Architecture using transparent latches for Networks-on-Chip
Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.)
pp. 45 - 50

CPSY2014-81
Implementation and Evaluation of An Accelerator based on Manymemory Network
Ryo Shimizu, Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST)
pp. 51 - 56

CPSY2014-82
Convolutional Neural Network Processing on An Accelerator based on Manymemory Network
Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST)
pp. 57 - 62

CPSY2014-83
[Fellow Memorial Lecture] Looking Back over My Researches on Flexible Hardware -- Reconfigurable Systems and FPGAs --
Toshinori Sueyoshi (Kumamoto Univ.)
pp. 63 - 68

CPSY2014-84
[Invited Talk] A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS
Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.)
pp. 69 - 74

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan