IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2014-11-26 - 2014-11-28 / Issue Date : 2014-11-19

RECONF2014-34
A study on automated arithmetic pipeline design on multi-FPGA systems
Yusuke Hirai, Katsuki Kyan, Makoto Arakaki (Univ. Ryukyus), Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. Ryukyus)
pp. 1 - 6

RECONF2014-35
Implementation of Multi-dimensional FPGA array HPC system-Vocalise for Numerical simulation and its Performance Evaluation
Jiang Li, Hiromasa Kubo, Satoru Yokota, Yuichi Ogishima, Masatoshi Sekine (TUAT)
pp. 7 - 12

RECONF2014-36
Time Analysis of Appling Back Gate Bias for Reconfigurable Architectures
Hayate Okuhara, Hideharu Amano (Keio Univ.)
pp. 13 - 18

RECONF2014-37
Mobile robot system based on hw/sw Complex System using 3D FPGA-Array System "Vocalise"
Hiromasa Kubo, Jiang Li, Satoru Yokota, Yuichi Ogishima, Masatoshi Sekine (TUAT)
pp. 19 - 24

RECONF2014-38
An Image Recognition System Learning Feature Regions with Vocalise
Satoru Yokota, Jiang Li, Hiromasa Kubo, Masatoshi Sekine (TUAT)
pp. 25 - 30

RECONF2014-39
Efficient FPGA resource allocation for HOG-based human detection
Masahito Oishi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 31 - 36

RECONF2014-40
[Invited Talk] Magnetic Resonance (MR) Safety of Implantable Medical Device: Current Status and Future Prospect
Kagayaki Kuroda (Tokai Univ.)
pp. 37 - 40

RECONF2014-41
[Invited Talk] Latest Development and Future Prospect of Mobile Display Technology
Yoshiharu Nakajima (JDI)
pp. 41 - 44

RECONF2014-42
Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator
Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 45 - 50

RECONF2014-43
Voice Recognition System using hw/sw Complex
Yuichi Ogishima, Jiang Li, Satoru Yokota, Hiromasa Kubo, Masatoshi Sekine (TUAT)
pp. 51 - 56

RECONF2014-44
Accelerating finite field arithmetic with a suitable word size
Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa (Nagasaki Univ.)
pp. 57 - 61

RECONF2014-45
[Invited Talk] A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS
Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.)
pp. 63 - 68

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan