Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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DC2014-26
Investigation of the area reduction of observation part and control part in TSV fault detection circuit
Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 3 - 8
DC2014-27
Analytical placement consistent with hierarchical structure constraints in analog floorplan
Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 9 - 13
DC2014-28
An efficient calculation of RTN-induced SRAM failure probability
Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)
pp. 15 - 20
DC2014-29
General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power
Shogo Yamasaki, Toshinobu Akazawa, Fengwei An, Hans Juergen Mattausch (Hiroshima Univ.)
pp. 21 - 26
DC2014-30
An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System
Masaharu Yamamoto, Anh-Tuan Hoang, Tetsushi Koide (Hiroshima Univ.)
pp. 27 - 32
DC2014-31
Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification
Koki Sugi, Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ.)
pp. 33 - 38
DC2014-32
Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images
Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ.)
pp. 39 - 44
DC2014-33
Design of Flip-Flop with Timing Error Tolerance
Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.)
pp. 45 - 50
DC2014-34
Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits
Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 51 - 56
DC2014-35
An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 57 - 62
DC2014-36
A hardware description method and sematics providing a timing constrant
Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 81 - 86
DC2014-37
Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework
Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu)
pp. 87 - 92
DC2014-38
Voltage Dependence of Single Event Transient Pulses on 65nm Silicon-on-Thin-BOX and Bulk Processes
Eiji Sonezaki, Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
pp. 93 - 97
DC2014-39
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs
Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 99 - 104
DC2014-40
A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures
Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 105 - 110
DC2014-41
A Method for Total Length and Length Difference Reduction for Set-Pair Routing
Yuta Nakatani, Atsushi Takahashi (Titech)
pp. 111 - 116
DC2014-42
High speed design of sub-threshold circuit by using DTMOS
Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.)
pp. 117 - 121
DC2014-43
Don't-Care Extension in Logic Synthesis for Error Tolerant Application
Tomoya Inaoka, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
pp. 123 - 128
DC2014-44
Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis
Junghoon Oh, Mineo Kaneko (JAIST)
pp. 129 - 134
DC2014-45
A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 135 - 140
DC2014-46
[Invited Talk]
Magnetic Resonance (MR) Safety of Implantable Medical Device: Current Status and Future Prospect
Kagayaki Kuroda (Tokai Univ.)
pp. 141 - 144
DC2014-47
[Invited Talk]
Latest Development and Future Prospect of Mobile Display Technology
Yoshiharu Nakajima (JDI)
pp. 145 - 148
DC2014-48
Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability
Mineo Kaneko (JAIST)
pp. 149 - 154
DC2014-49
On implicit enumeration of vector pairs for synthesizing index generator
Yusuke Matsunaga (Kyushu Univ.)
pp. 161 - 165
DC2014-50
[Invited Talk]
A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS
Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.)
pp. 167 - 172
DC2014-51
Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open
Masayuki Arai (Nihon Univ.), Yuta Nakayama, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 173 - 178
DC2014-52
A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors
Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.)
pp. 179 - 184
DC2014-53
A Test Point Insertion Method to Reduce Capture Power Dissipation
Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
pp. 185 - 190
DC2014-54
A Multi Cycle Capture Test Generation Method to Reduce Capture Power Dissipation
Hiroshi Yamazaki, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
pp. 191 - 196
DC2014-55
A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning
Koki Ito, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.)
pp. 197 - 202
DC2014-56
Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 203 - 208
DC2014-57
A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures
Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 209 - 214
DC2014-58
A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations
Shunya Hosaka, Hiroshi Saito (Univ. Aizu)
pp. 215 - 220
DC2014-59
Energy evaluation of bit-write reduction method based on state encoding limiting maximum and minimum Hamming distances for non-volatile memories
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 221 - 226
DC2014-60
Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 227 - 232
DC2014-61
Optimization for gate-level pipelined self-synchrnous circuit
Atsushi Ito, Makoto Ikeda (Univ. of Tokyo)
pp. 233 - 238
DC2014-62
The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals
Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Hiroshi Makino (OIT), Kazutami Arimoto (Okayama Prefectural Univ.)
pp. 239 - 244
DC2014-63
On-chip delay measurement for FPGAs
Kentaro Abe, Yousuke Miyake, Seiji Kajihara, Yasuo Sato (KIT)
pp. 245 - 250
DC2014-64
A Method of Burn-in Fail Prediction of LSIs Based on Supervised Learning Using Cluster Analysis
Shogo Tetsukawa, Seiya Miyamoto, Satoshi Ohtake (Oita Univ.), Yoshiyuki Nakamura (Renesas)
pp. 251 - 256
DC2014-65
Some Studies of n-Fault-Tolerant System with Voting Switches
Hitoshi Iwai
pp. 257 - 262
DC2014-66
An analytic evaluation on soft error immunity enhancement due to temporal triplication
Ryutaro Doi, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
pp. 263 - 268
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.