IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2015-05-14 / Issue Date : 2015-05-07

VLD2015-1
A minimum test pattern set generation for large circuits
Yusuke Matsunaga (Kyushu Univ.)
pp. 1 - 6

VLD2015-2
Use of the subgradient method to minimize half perimeter wirelength with consideration of cell overlap in analytical placement
Hiroyuki Iwasaki, Hiroshi Miyashita (The Univ. of Kitakyushu)
pp. 7 - 12

VLD2015-3
NP-completeness of Routing Problem with Bend Constraint
Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech)
pp. 13 - 18

VLD2015-4
Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits
Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)
pp. 31 - 36

VLD2015-5
[Invited Talk] Trends and Future Challenges of Nano-electronics R&D in Japan
Seiichiro Kawamura (JST)
p. 37

VLD2015-6
Power Analysis Method for a Lightweight Block Cipher Simon
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
pp. 45 - 50

VLD2015-7
AES Encryption Circuit against Clock Glitch based Fault Analysis
Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ)
pp. 51 - 55

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan