IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 115, Number 440

Silicon Device and Materials

Workshop Date : 2016-01-28 / Issue Date : 2016-01-21

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Table of contents

SDM2015-120
[Invited Talk] Experimental Study on Carrier Transport Properties in Extremely-Thin Body Ge-on-Insulator (GOI) p-MOSFETs with GOI Thickness Down to 2 nm
Xiao Yu, Jian Kang, Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo)
pp. 1 - 4

SDM2015-121
[Invited Talk] Carrier Transport Analysis of High-Performance Poly-Si Nanowire Transistor Fabricated by Advanced SPC with Record-High Electron Mobility
Minoru Oda, Kiwamu Sakuma, Yuuichi Kamimuta, Masumi Saitoh (Toshiba Corp.)
pp. 5 - 8

SDM2015-122
[Invited Talk] Understanding of BTI for Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yuki Ishikawa, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo (AIST)
pp. 9 - 12

SDM2015-123
[Invited Talk] Van der Waals Junctions of Layered 2D Materials for Functional Devices
Tomoki Machida, Rai Moritani, Yohta Sata, Takehiro Yamaguchi, Miho Arai, Naoto Yabuki, Sei Morikawa, Satoru Masubuchi (Univ. of Tokyo), Keiji Ueno (Saitama Univ.)
pp. 13 - 16

SDM2015-124
[Invited Talk] CMOS photonics technologies based on heterogeneous integration on Si
Mitsuru Takenaka, Younghyun Kim, Jaehoon Han, Jian Kan, Yuki Ikku, Yongpeng Cheng, Jinkwon Park, SangHyeon Kim, Shinichi Takagi (Univ. of Tokyo)
pp. 17 - 20

SDM2015-125
[Invited Talk] 2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes
Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas)
pp. 21 - 25

SDM2015-126
[Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme
Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba)
pp. 27 - 30

SDM2015-127
[Invited Talk] Super Steep Subthreshold Slope PN-Body Tied SOI FET with Ultra Low Drain Voltage
Jiro Ida (Kanazawa Institute of Technology)
pp. 31 - 34

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan