Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2014] | [2015] | [2016] | [2017] | [2018] | [2019] | [2020] | [Japanese] / [English]
RECONF2017-22
Pattern-matching-based game strategies and the strategy difference in pattern sizes
Masataka Nakano, Yoshiki Yamaguchi (Univ. of Tsukuba)
pp. 1 - 6
RECONF2017-23
A thorough investigation of FPGA performance for PCIe Gen3 communication
Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba)
pp. 7 - 12
RECONF2017-24
(See Japanese page.)
pp. 13 - 18
RECONF2017-25
A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme
Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT)
pp. 19 - 24
RECONF2017-26
A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.)
pp. 25 - 30
RECONF2017-27
Hardware acceleration for holographic memories on optically reconfigurable gate arrays
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
pp. 31 - 36
RECONF2017-28
Proplsal of reconfigurable system LSI with BiCS technology
-- Application to combination logic, FF, CMOS circuit and FPGA --
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shouto Tamai (Oi Electric), Takumi Sato (Japan Business Systems)
pp. 37 - 42
RECONF2017-29
Performance analysis of Mono-Instruction Set Computer using VTR
Hiroki Shinba, Minoru Watanabe (Shizuoka Univ.)
pp. 43 - 46
RECONF2017-30
[Invited Talk]
Scalable and convertible FPGA DNN accelerator
Shinichi Suto, Takato Yamada (LeapMind)
pp. 47 - 49
RECONF2017-31
GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato (Tokyo Inst. of Tech.)
pp. 51 - 56
RECONF2017-32
High-speed Calculation of k-means Clustering Using FPGA and its Application to Pick and Place Machine
Shogo Nakamura, Hiroki Ebara, Kenji Kanazawa (Univ. of Tsukuba), Noriyuki Aibe (Keio Univ.), Moritoshi Yasunaga (Univ. of Tsukuba)
pp. 57 - 62
RECONF2017-33
[Invited Talk]
Increasing Productivity Using Xilinx Development Tools
Louie Valena (Xilinx)
pp. 63 - 68
RECONF2017-34
(See Japanese page.)
pp. 69 - 74
RECONF2017-35
A case study of High-level Synthesis Using Higher-order Function on Functional Language
Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 75 - 80
RECONF2017-36
Implementing RISC-V with a Python-Based High-Level Synthesis Compiler
Ryouzaburo Suzuki, Hiroaki Kataoka (Sinby)
pp. 81 - 86
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.