IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2017-11-06 - 2017-11-07 / Issue Date : 2017-10-30

RECONF2017-37
FPGA Implementation of Pattern Matching of PCRE for NIDS and its Acceleration and Memory Saving
Masahiro Fukuda, Yasushi Inoguchi (JAIST)
pp. 1 - 6

RECONF2017-38
(See Japanese page.)
pp. 7 - 12

RECONF2017-39

Ryo Kamasaka, Taisei Segawa, Yuichiro Shibata (Nagasaki Univ.)
pp. 13 - 18

RECONF2017-40
Real Chip Evaluation of a Variable Pipelined Coarse-Grained Reconfigurable Array
Naoki Ando, Takuya Kojima, Hideharu Amano (Keio Univ.)
pp. 19 - 24

RECONF2017-41
(See Japanese page.)
pp. 25 - 30

RECONF2017-42
Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking
Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ)
pp. 31 - 36

RECONF2017-43
(See Japanese page.)
pp. 37 - 42

RECONF2017-44
(See Japanese page.)
pp. 43 - 48

RECONF2017-45
IoT Platform using an MCU-FPGA Hybrid System and Feasibility Study of Wireless Configuration
Ryota Suzuki, Hironori Nakajo (TUAT)
pp. 49 - 54

RECONF2017-46
Calculation method of exponential function on FPGAs using high-radix STL method
Yasufumi Fujiwara, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
pp. 55 - 59

RECONF2017-47
(See Japanese page.)
pp. 61 - 66

RECONF2017-48
(See Japanese page.)
pp. 67 - 71

RECONF2017-49
[Keynote Address] Theory and applications of dynamical sparse modeling
Masaaki Nagahara (Univ. of Kitakyushu)
pp. 73 - 74

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan