Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2017-62
Yugo Yamauchi, Kazusa Musha (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.)
pp. 1 - 6
VLD2017-63
All Binarized Conventional Neural Network and its Implementation on an FPGA
-- FPT2017 Design Competition Report --
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech)
pp. 7 - 11
VLD2017-64
An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL
Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech)
pp. 13 - 18
VLD2017-65
Kazutaka Ogihara (Fujitsu Lab.)
pp. 19 - 24
VLD2017-66
Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 25 - 29
VLD2017-67
(See Japanese page.)
pp. 31 - 36
VLD2017-68
Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs
Kaori Tajima, Masahiro Inoue, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.)
pp. 37 - 42
VLD2017-69
Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set
Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 43 - 48
VLD2017-70
Examination of the Normally-off using the stack circuit
Kenji Sakamura (OPUGS), Kazutami Arimoto, Isao Kayano, Tomoyuki Yokogawa (OPU)
pp. 49 - 51
VLD2017-71
(See Japanese page.)
pp. 53 - 58
VLD2017-72
(See Japanese page.)
pp. 59 - 63
VLD2017-73
Integrated Machine Code Monitor on FPGA
Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.)
pp. 65 - 70
VLD2017-74
Daichi Tanaka, Antoniette Mondigo, Kentaro Sano, Satoru Yamamoto (Tohoku Univ)
pp. 71 - 76
VLD2017-75
Distributed Memory Architecture for High-Level Synthesis from Erlang
Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM)
pp. 77 - 82
VLD2017-76
FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language
Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT)
pp. 83 - 88
VLD2017-77
Overview of an HLS Framework Surpporting IoT/CPS Development
Daichi Teruya, Hironori Nakajo (TUAT)
pp. 89 - 94
VLD2017-78
Automatic Conversion from Snort PCRE to Verilog HDL
Masahiro Fukuda, Yasushi Inoguchi (JAIST)
pp. 95 - 100
VLD2017-79
Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor
Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.)
pp. 101 - 106
VLD2017-80
A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
pp. 107 - 112
VLD2017-81
Total-ionizing-dose tolerance of an optically reconfigurable gate array
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
pp. 113 - 117
VLD2017-82
FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights
Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 119 - 124
VLD2017-83
Accelerating Sequential Learning Algorithm OS-ELM Using FPGA-NIC
Mineto Tsukada, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
pp. 133 - 138
VLD2017-84
Accelerating Serialization Protocols for Network-Attached FPGAs
Takuma Iwata, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
pp. 139 - 144
VLD2017-85
(See Japanese page.)
pp. 145 - 150
VLD2017-86
Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs
Yoshio Murata, Hironori Nakajo (TUAT)
pp. 151 - 156
VLD2017-87
Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation
Mitsuyoshi Iwatsuji, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 163 - 168
VLD2017-88
Mutant Generation of Performance Tests for LLVM Back-Ends
Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas)
pp. 169 - 174
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.