IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 117, Number 379

Reconfigurable Systems

Workshop Date : 2018-01-18 - 2018-01-19 / Issue Date : 2018-01-11

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Table of contents

RECONF2017-50

Yugo Yamauchi, Kazusa Musha (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.)
pp. 1 - 6

RECONF2017-51
All Binarized Conventional Neural Network and its Implementation on an FPGA -- FPT2017 Design Competition Report --
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech)
pp. 7 - 11

RECONF2017-52
An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL
Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech)
pp. 13 - 18

RECONF2017-53

Kazutaka Ogihara (Fujitsu Lab.)
pp. 19 - 24

RECONF2017-54

Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 25 - 29

RECONF2017-55
(See Japanese page.)
pp. 31 - 36

RECONF2017-56
Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs
Kaori Tajima, Masahiro Inoue, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.)
pp. 37 - 42

RECONF2017-57
Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set
Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 43 - 48

RECONF2017-58
Examination of the Normally-off using the stack circuit
Kenji Sakamura (OPUGS), Kazutami Arimoto, Isao Kayano, Tomoyuki Yokogawa (OPU)
pp. 49 - 51

RECONF2017-59
(See Japanese page.)
pp. 53 - 58

RECONF2017-60
(See Japanese page.)
pp. 59 - 63

RECONF2017-61
Integrated Machine Code Monitor on FPGA
Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.)
pp. 65 - 70

RECONF2017-62

Daichi Tanaka, Antoniette Mondigo, Kentaro Sano, Satoru Yamamoto (Tohoku Univ)
pp. 71 - 76

RECONF2017-63
Distributed Memory Architecture for High-Level Synthesis from Erlang
Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM)
pp. 77 - 82

RECONF2017-64
FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language
Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT)
pp. 83 - 88

RECONF2017-65
Overview of an HLS Framework Surpporting IoT/CPS Development
Daichi Teruya, Hironori Nakajo (TUAT)
pp. 89 - 94

RECONF2017-66
Automatic Conversion from Snort PCRE to Verilog HDL
Masahiro Fukuda, Yasushi Inoguchi (JAIST)
pp. 95 - 100

RECONF2017-67
Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor
Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.)
pp. 101 - 106

RECONF2017-68
A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
pp. 107 - 112

RECONF2017-69
Total-ionizing-dose tolerance of an optically reconfigurable gate array
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
pp. 113 - 117

RECONF2017-70
FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights
Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 119 - 124

RECONF2017-71
Accelerating Sequential Learning Algorithm OS-ELM Using FPGA-NIC
Mineto Tsukada, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
pp. 133 - 138

RECONF2017-72
Accelerating Serialization Protocols for Network-Attached FPGAs
Takuma Iwata, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
pp. 139 - 144

RECONF2017-73
(See Japanese page.)
pp. 145 - 150

RECONF2017-74
Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs
Yoshio Murata, Hironori Nakajo (TUAT)
pp. 151 - 156

RECONF2017-75
Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation
Mitsuyoshi Iwatsuji, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 163 - 168

RECONF2017-76
Mutant Generation of Performance Tests for LLVM Back-Ends
Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas)
pp. 169 - 174

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan