IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2019-01-30 - 2019-01-31 / Issue Date : 2019-01-23

VLD2018-72
On Delay Optimization for Improving General Synchronous Performance
Eijiro Sassa, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
pp. 1 - 6

VLD2018-73
Proposal of reduction method of calculations by using Leading Zero in the Extended Euclidean Algorithm
Masaki Ogino, Yuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 7 - 12

VLD2018-74
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo)
pp. 13 - 18

VLD2018-75
A CNN with a Noise Addition for Efficient Implementation on an FPGA
Atsuki Munakata, Shimpei Satou, Hiroki Nakahara (Tokyo Tech)
pp. 19 - 24

VLD2018-76
Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation
Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech)
pp. 25 - 30

VLD2018-77
Study of stacked full adder circuit with fabrication technology of 3D flash memory
Fumiya Suzuki, Sigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 31 - 35

VLD2018-78
Design and implementation of FPGA measurement feedback system in Coherent Ising Machine
Toshimori Honjo, Takahiro Inagaki, Kensuke Inaba, Takuya Ikuta, Hiroki Takesue (NTT)
pp. 37 - 42

VLD2018-79
An integrated development platform of FPGA for ROS-based autonomous mobile robot
Sou Tamura, Yasuhiro Nitta, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ)
pp. 43 - 48

VLD2018-80
Implementation of Image Processing Algorithm Aiming for Autonomous Car Using FPGA
Koki Honda, Wei Kaije, Hideharu Amano (Keio Univ.)
pp. 49 - 53

VLD2018-81
[Invited Talk] Large Scale PC Cluster Technologies -- 20 years and future perspectives perspectives --
Kohta Nakashima (Fujitsu lab.)
pp. 55 - 57

VLD2018-82
The Evaluation of Partial Reconfiguration for FiCSW
Miho Yamakura, Keita Azegami, Kazusa Musha, Hideharu Amano (Keio Univ.)
pp. 59 - 64

VLD2018-83
A Deduplication Mechanism for Effectively-once Semantics Using FPGA NIC
Koji Suzuki, Koya Mitsuzuka, Takuma Iwata, Hiroki Matsutani (Keio Univ.)
pp. 65 - 70

VLD2018-84
Preliminary Evaluation of Parallel Processing Performance on MPI Runtime Environment for Android OS
Masahiro Nissato, Hiroki Sugiyama, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.)
pp. 71 - 76

VLD2018-85
A Case for Unsupervised Abnormal Behavior Detection Using Multiple Online Sequential Learning Cores
Rei Ito, Mineto Tsukada (Keio Univ), Masaaki Kondo (Univ Tokyo), Hiroki Matsutani (Keio Univ)
pp. 77 - 82

VLD2018-86
Area and Performance Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core
Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
pp. 83 - 88

VLD2018-87
(See Japanese page.)
pp. 95 - 99

VLD2018-88
Preliminary evaluation of special instruction implementation methods by high level synthesis
Ryodai Iwamoto, Naoki Fujieda, Shuichi Ichikawa, Joji Sakamoto (TUT)
pp. 101 - 106

VLD2018-89
(See Japanese page.)
pp. 107 - 112

VLD2018-90
(See Japanese page.)
pp. 113 - 118

VLD2018-91

Takefumi Miyoshi (TOYOTA ITC)
pp. 119 - 124

VLD2018-92
An implementation and evaluation of Lattice-Boltzmann Method on Intel Programmable Accelerator Card
Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN)
pp. 125 - 130

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan