IEICE Technical Report

Online edition: ISSN 2432-6380

Volume 121, Number 388

Dependable Computing

Workshop Date : 2022-03-01 / Issue Date : 2022-02-22

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Table of contents

DC2021-64
Design of Successive Approximation ADC using Standard Cell Design Flow
Hiroshi Hirano, Satoshi Komatsu (Tokyo Denki Univ.)
pp. 1 - 6

DC2021-65
Multi-process Automatic Generation System for ADC Using Standard cell
Takumi Fukushima, Satoshi Komatsu (Tokyo Denki Univ.)
pp. 7 - 12

DC2021-66
(See Japanese page.)
pp. 13 - 17

DC2021-67
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement
Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT)
pp. 18 - 23

DC2021-68
Applicability Evaluation of the Delay Testable Circuit to PUF
Eisuke Ohama, Haruka Chino, Hiroyuki Yotuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 24 - 29

DC2021-69
(See Japanese page.)
pp. 30 - 32

DC2021-70
A TMR-Based Approximate Corrector for Fail-Operational Systems
Mitsuyoshi Ashida, Tomoo Inoue, Hideyuki Ichihara (City Univ)
pp. 33 - 38

DC2021-71
Delay Fault Test Pattern Generation of Fault Tolerant Design Using Approximate Computing
Koji Makino, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 39 - 44

DC2021-72
A Logic Locking Method based on SFLL-hd at Register Transfer Level
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.)
pp. 45 - 50

DC2021-73
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability
Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech)
pp. 51 - 56

DC2021-74
SAT-based LFSR Seed Generation for Delay Fault BIST
Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.)
pp. 57 - 62

DC2021-75
State assignment method to improve transition fault coverage for controllers including invalid states
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)
pp. 63 - 68

DC2021-76
Evaluation of Don't Care Filling Method of Control Signals to Enhance Fault Diagnosability for Logic and Timing Fault
Kohei Tsuchibuchi, Xu Haofeng, Yuya Chida, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ)
pp. 69 - 74

DC2021-77
An Estimation Method of Defect Types for Multi-cycle Capture Testing Using Artificial Neural Networks and Fault Detection Information
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai, Yukari Yamauchi (Nihon Univ.)
pp. 75 - 80

DC2021-78
(See Japanese page.)
pp. 81 - 86

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan