Online edition: ISSN 2432-6380
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VLD2024-103
Error Correation Methods with Node Redundancy Considering Node Level in DMFB
Koki Suzuki, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT)
pp. 1 - 6
VLD2024-104
Speeding Up a Routing Method Considering Droplet Division on MEDA Biochips by Dijkstra's Method
Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT)
pp. 7 - 12
VLD2024-105
Fast Droplet Routing Algorithm for MEDA-Based DMFB
Emuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi (Science Tokyo)
pp. 13 - 18
VLD2024-106
A Motif Extraction Method By Subsequence Classification Using Random Forests
Jigen Murata, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, Shinobu Nagayama (HCU)
pp. 19 - 24
VLD2024-107
Placement of Items to be Picked for Products in Manufacturing Industries
Natsumi Nakayama, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, Shinobu Nagayama (HCU)
pp. 25 - 30
VLD2024-108
A Note on 4-Layer U-shape Bottleneck Channel Routing
Yo Sakakura, Satoshi Tayu, Masayuki Shimoda, Atsushi Takahashi (Science Tokyo)
pp. 31 - 36
VLD2024-109
Analog Primitive Cell Identification for Large-scale Analog Circuit with Graph Neural Network
Chen Geng, Shigetoshi Nakatake (Univ. of Kitakyushu), Nobuto Ono, Katsuya Nishioka, Shigeya Yamaguchi, Takahiro Hikida, Noriteru Matsubara, Yukichi Todoroki (Jedat)
pp. 37 - 42
VLD2024-110
A Study on Data Transfer from Synchronous Circuits to Asynchronous Circuits Using AXI Lite
Shogo Semba, Hiroshi Saito (UoA)
pp. 43 - 48
VLD2024-111
Design and evaluation of image processing architecture based on Network on Chip
Hayato Miyoshi, Rento Yoshihara, Ryuya Kadota, Kanto Kawakami, Masafumi Kondo (Okayama Science Univ.)
pp. 49 - 54
VLD2024-112
Implementation of the Sort Instruction in a RISC-V Processor Using Chipyard
Daiki Masuda, Yoshinori Takeuchi (Kindai Univ.)
pp. 55 - 60
VLD2024-113
Efficient and Accurate SC Arithmetic Circuits Using Bit Manipulation Based on Interval Partitioning of Bit Strings
Yota Yanagida, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 61 - 65
VLD2024-114
An efficient LSI implementation of popcount for convolution operations in binarized neural networks
Reiji Kikuchi, Kazuhito Ito (Saitama Univ.)
pp. 66 - 71
VLD2024-115
An implementation of convolution and pooling operations in binarized neural networks on register-bridge architecture LSI
Yuichiro Iwai, Kazuhito Ito (Saitama Univ.)
pp. 72 - 77
VLD2024-116
Application of Single-Base RNS Montgomery Multiplication Algorithm
Shinichi Kawamura (AIST), Yuichi Komano (CIT)
pp. 78 - 83
VLD2024-117
Implementation Method and Circuit Fabrication for Photonic Circuits of Symmetric Key Cryptography
Junko Takahashi, Shota Kita, Akihiko Shinya (NTT), Kazumaro Aoki (Bunkyo Univ), Koji Chida (Gunma Univ), Fumitaka Hoshino (Univ. of Nagasaki)
pp. 84 - 89
VLD2024-118
Re-evaluation of Tamper-resistant Designs Using a Side-channel Attack Platform for Netlist
Ryoma Katsube, Tomoaki Ukezono (Fukuoka Univ)
pp. 90 - 94
VLD2024-119
[Memorial Lecture]
A Study on SQA Acceleration Using Multi-FPGA for Route Optimization of Large-scale Mobile Robots System
Thinh NguyenQuang (Tohoku University), Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto (Sharp Corporation), Hasitha Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki (Tohoku University)
p. 95
VLD2024-120
Single-Source Shortest Path FPGA Accelerator Using Multiple Parallel Searches with High-Level Synthesis and Linked List Implementation
Haopeng Meng, Kazutoshi Wakabayashi, Makoto Ikeda (The University of Tokyo)
pp. 96 - 101
VLD2024-121
A Study on Software-Hardware Partitioning Method for SoC FPGAs
Koki Murano, Ryo Yamamoto, Takahiro Morii, Osamu Toyama (Mitsubishi Electric Corp.)
pp. 102 - 107
VLD2024-122
A method for mapping and scheduling of operations targeting register-bridge architecture LSIs with memory accesses
Sota Akashi, Kazuhito Ito (Saitama Univ.)
pp. 108 - 113
VLD2024-123
N/A
Ryuta Kawamura, Ryusei Eda, Hibiki Nakanishi, Nozomu Togawa (Waseda Univ.)
pp. 114 - 119
VLD2024-124
N/A
So Iomori, Ryusei Eda (Waseda Univ.), Ryoichi Kida, Tsuneo Ogasawara (LAC), Nozomu Togawa (Waseda Univ.)
pp. 120 - 125
VLD2024-125
Performance Evaluation of Heart Sound Classification Using CNN, BNN, TNN, and SNN
Reo Taniguchi, Haruto Furuta, Yutaro Yamanaka, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 126 - 131
VLD2024-126
MTJ-PUF with Response Reuse and Evaluation of Machine Learning Attack Resistance
Taiki Tsukada, Kimiyoshi Usami (SIT)
pp. 132 - 137
VLD2024-127
Cost reduction of fine-grained power domain partitioning circuits enabling hardware trojan detection
Takahiro Ishikawa, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.), Michihiro Shintani (Kyoto Inst. of Tech.), Jun Shiomi (Osaka Univ.)
pp. 138 - 143
VLD2024-128
Development of Hardware Trojans using Transistor Characteristics in Low Temperature Environments
Ayano Takaya, Ryuichi Nakajima (Kyoto Inst. of Tech.), Jun Shiomi (Osaka Univ.), Michihiro Shintani (Kyoto Inst. of Tech.)
pp. 144 - 149
VLD2024-129
Study on Constitution Method of Multiple PLLs for Fault Injection Countermeasures to Cryptographic Modules
Hikaru Nishiyama (AIST/NAIST), Daisuke Fujimoto, Yuichi Hayashi (NAIST)
pp. 150 - 154
VLD2024-130
Pipeline design of LUT-reduction based butterfly unit for high-speed NTT
Riku Koizumi, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
pp. 155 - 159
VLD2024-131
Performance Evaluation of FPGA Evaluation Boards in Cryogenic Environments
Tomoki Takashima, Akimasa Saito, Masashi Imai (Hirosaki Univ.)
pp. 160 - 165
VLD2024-132
Integration of a Quantum Annealing Simulator and a Circuit Simulator and Evaluation of Their Usefulness
Akimasa Saito, Masashi Imai (Hirosaki Univ.)
pp. 166 - 171
VLD2024-133
Miniature Multimodal Olfactory Device with 3D MSS-CMOS Chip Stack
Naru Kato, Kotaro Naruse, Takuma Matsumori, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose (Osaka Univ.), Gaku Imamura (Osaka Univ./NIMS), Genki Yoshikawa (Tsukuba Univ./NIMS), Noriyuki Miura (Osaka Univ.)
pp. 172 - 175
VLD2024-134
Interpretable Deep Learning-based Side-channel Analysis Using Kolmogorov-Arnold Networks
Kota Yoshida (Ritsumeikan Univ.), Sengim Karayalcin (Leiden Univ.), Stjepan Picek (Radboud Univ.)
pp. 176 - 181
VLD2024-135
Implementation of Side-channel-attack Environment against In-vehicle ECUs Using CAN Packet Monitoring for Triggering Waveform Acquisition
Tomoe Kato, Yuta Fukuda, Mizuki Nagahisa, Masato Okuda, Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.)
pp. 182 - 187
VLD2024-136
Optimizing Deep Learning Based Side-Channel Attacks Methods by Preprocessing Based on Autoencoder
Masaki Morita, Takuya Kojima, Haruto Ishii, Hideki Takase, Hiroshi Nakamura (UTokyo)
pp. 188 - 193
VLD2024-137
Hardware-Assisted IoT Security: Real-Time DDoS Detection through Power Side-Channel Analysis
Qingyu Zeng, Mingyu Yang, Yuko Hara (Science Tokyo)
pp. 194 - 199
VLD2024-138
Quantitative Comparison of Fault Attack Vulnerability Detection Tools
Shoei Nashimoto (Mitsubishi Electric)
pp. 200 - 205
VLD2024-139
Hybrid and Hierarchical Detection Flow for Hardware Trojans
Takafumi Oki, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.)
pp. 206 - 211
VLD2024-140
Scalability Evaluation of Sensing Security Technology for Surveillance Cameras Using Device Inherence
Kotaro Naruse, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.)
pp. 212 - 213
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.