IEICE Technical Report

Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2025-09-18 - 2025-09-19 / Issue Date : 2025-09-11

RECONF2025-50
[Invited Talk] Toward AI Applications: Large-Scale FPGA System Design Using OneAPI
Hasitha Muthumala Waidyasooriya (Tohoku Univ.)
pp. 1 - 4

RECONF2025-51
From Algorithm to FPGA: Design and Verification with MATLAB and Simulink
Hiroyuki Kawai (MathWorks Japan)
p. 5

RECONF2025-52
ESSPER2: FPGA Cluster as a research platform for quantum error correction and HPC
Kentaro Sano, Tomohiro Ueno (RIKEN), Fuga Kato, Kazuya Mochizuki, Katsuhiko Ota, Nozomu Matsunaga (IBEX)
pp. 6 - 11

RECONF2025-53
[Invited Talk] Report of the FPGA AI Hackathon in HotSPA2025
Hideharu Amano, Takao Goto, Mizuho Nitami, Atsutake Kosuge, Makoto Ikeda (U. of Tokyo)
pp. 12 - 13

RECONF2025-54
[Invited Talk] FPGA AI Design Hackathon First-place Solution
Ryoga Yuzawa, Tasuku Takagi, Motoyuki Sugioka (Sony)
pp. 14 - 19

RECONF2025-55
[Invited Talk] Acceleration of YOLOv5n on FPGA -- Implementation Report through Hackathon --
Shota Ikari, Hisako Ito (UTokyo)
pp. 20 - 21

RECONF2025-56
[Invited Talk] Accelerating YOLOv3-tiny on an MPSoC FPGA -- A Report from an FPGA-AI Design Hackathon --
Musashi Otsuka, Atsuhiro Okamoto, Takayuki Suyama (OIT)
pp. 22 - 27

RECONF2025-57
Development of an easy-to-handle and two wheeled self-balancing robot utilizing an FPGA
Daichi Kumagai, Komei Kodera (Science Tokyo), Yuya Iwata (IBEX Technology), Kenji Kise (Science Tokyo)
pp. 28 - 33

RECONF2025-58
Design and Parallel Performance Evaluation of a Multi-FPGA SQA Accelerator for Route Optimization in Large-Scale AGV Systems
NGuyen Quang Thinh, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto (Sharp), Hasitha Muthumala Waidyasooriya, Kosei Nishio, Masanori Hariyama, Masaru Hitomi, Kenta Sawamura, Masayuki Ohzeki (Tohoku University)
pp. 34 - 39

RECONF2025-59
Design Considerations for an F-tile Ethernet Communication Controller in the OFS Environment
Junsei Tabata, Yasunori Osana (Kumamoto Univ.)
pp. 40 - 45

RECONF2025-60
LUT-based expansion method of a D-FF resource inside an FPGA
Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 46 - 49

RECONF2025-61
Recovery from radiation-degradation of optical configuration circuits on an optically reconfigurable gate array VLSI
Seiji Ohashi, MInoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 50 - 54

RECONF2025-62
Radiation-Hardened JTAG Interface for OpenOCD-Compliant Optically Reconfigurable Gate Array VLSI
Naoki Nagamine, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 55 - 60

RECONF2025-63
[Invited Talk] Computer Science Supporting the Realization of Real-Time Combinatorial Optimization Systems Using Simulated Bifurcation Machines
Tomoya Kashimata (Toshiba)
pp. 61 - 66

RECONF2025-64
Design and implementation of a high-performance RISC-V SoC for FPGAs with Linux support
Yuki Yagi, Kenji Kise (Science Tokyo)
pp. 67 - 72

RECONF2025-65
Enhanced PAE Cell Architecture for eFPGA IP with Reduced Logic Cell Area
Tatsuya Sasaki, Souta Kohata, Ryo Iwasaki, Masahiro Iida (Kumamoto Univ.)
pp. 73 - 78

RECONF2025-66
Comparative Evaluation of CPU, FPGA, and GPU for CRS Conversion in Sparse Matrix Computation
Tomoya Yokono, Keisuke Sugiura, Yoshiki Yamaguchi (Tsukuba Univ.)
pp. 79 - 84

RECONF2025-67
Exploring AXI4 Transaction Support in RIKEN CGRA Architecture
Jiaheng Liu, Boma Adhi, Chenlin Shi (R-CCS), Shinobu Miwa (UEC), Kentaro Sano (R-CCS)
pp. 85 - 90

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan