Online edition: ISSN 2432-6380
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ICD2025-37
Experimental Custom LSI Design and Evaluation with Open-Source EDA
Toshihiro Katashita, Yasuhiro Ogasahara, Yuuta Fukuda, Yohei Hori, Masakazu Hioki (AIST)
pp. 1 - 5
ICD2025-38
LUT Optimization of Approximate Multiplier on FPGA for Error Reduction
Shinji Kimura (Waseda Univ.), Takashi Horiyama (Hokkaido Univ.)
pp. 6 - 11
ICD2025-39
Automatic Partitioning of Multiple-Precision Arithmetic and Optimization of Data Paths
Yusuke Suzuki, Makoto Ikeda (UTokyo)
pp. 12 - 17
ICD2025-40
Scalable FPGA Delta-Stepping Accelerator Design for Parallel Single-Source Shortest Path Problem using High-Level Synthesis
Meng Haopeng, Kazutoshi Wakabayashi, Makoto Ikeda (UTokyo)
pp. 18 - 23
ICD2025-41
On the Acceleration of Multiple Target Test Generation Using Necessary and Sufficient Conditions for Fault Detection
Tao Sawada, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)
pp. 24 - 29
ICD2025-42
Parallel Patitioning Testing for a Set-Operation Processor with Near-Memory Architecture
Wang Ziyang, Yamamoto Ryusuke, Wang Senling, Kai Hiroshi, Higami Yoshinobu, Takahashi Hiroshi (Ehime Univ.)
pp. 30 - 35
ICD2025-43
A Register Binding Method for Diagnosability Based on Dummy Operations
Shuji Kubokura, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ), Masayoshi Yoshimura (KSU)
pp. 36 - 41
ICD2025-44
Evaluation of the Effectiveness of Instruction-Level Pseudorandom Testing on a RISC-V Processor
Shinnosuke Hamamura, Satoshi Ohtake (Oita Univ.)
pp. 42 - 47
ICD2025-45
[Keynote Address]
Hideki Wakabayashi (Kumamoto Univ.)
pp. 48 - 51
ICD2025-46
Generation of a Standard-Cell Library Supporting Forward Body Biasing at Cryogenic Temperatures and Performance Evaluation on a RISC Processor
Shin Taniguchi, Zhipeng Liang, Hajime Tanakayama (KIT), Jun Shiomi (UOsaka), Michihiro Shintani (KIT)
pp. 52 - 57
ICD2025-47
Chip Design of an Ultra-Parallel TSV Bus Communication Scheme for High-Efficiency Data Transfer in Three-Dimensional Stacked LSI Systems
Yuto Shiota, Fuchino Kakeru, Fukushima Shouma (Kumamoto Univ.), Kuboki Takeshi (Hiroshima Univ.), Aoyagi Masahiro, Ohkawa Takeshi (Kumamoto Univ.)
pp. 58 - 63
ICD2025-48
Implementation of an Automated Program for Custom Instructions in Rocket Chip Using Four Approaches
Takaharu Kitayama, Yoshinori Takeuchi (Kindai Univ.)
pp. 64 - 69
ICD2025-49
Highly Accurate Extraction of Random Telegraph Noise Features in TaOx-based ReRAM for CiM Applications
Yushi Abarra, Naoko Misawa, Chihiro Matsui, Ken Takeuchi (Univ. Tokyo)
pp. 70 - 73
ICD2025-50
Changes in Read Current and RTN Frequency due to Read-disturb in 40nm TaOx ReRAM
Shota Suzuki, Naoko Misawa, Chihiro Matsui, Ken Takeuchi (The Univ. of Tokyo)
pp. 74 - 79
ICD2025-51
Column-wise Weight Inversion Method to Reduce MAC Value Error due to Data-retention in ReRAM-based Computation-in-Memory
Naoko Misawa, Yusuke Izume, Yusuke Hirata (Univ. Tokyo), Masahiro Morimoto, Takeshi Ohara (NTCJ), Chihiro Matsui, Ken Takeuchi (Univ. Tokyo)
pp. 80 - 83
ICD2025-52
Fine-tuning Method using LoRA with Iterative Error Injection to make ViT Computation-in-Memory Tiny and Robust to Errors
Naoko Misawa, Ruiqi Zhang, Tao Wang, Chihiro Matsui, Ken Takeuchi (Univ. Tokyo)
pp. 84 - 86
ICD2025-53
[Invited Talk]
Circuit Design Connecting Primary, Secondary, and Higher Education
-- Important Things that are Invisible --
Yohei Ishikawa (Ariake KOSEN)
pp. 87 - 92
ICD2025-54
[Invited Talk]
Development of AI trigger on FPGA for High Energy Physics experiments
Junpei Maeda (Kobe Univ.)
p. 93
ICD2025-55
Layout Optimization of FPGA-based DTM PUF for Compact Implementation
Yuta Fukuda (AIST/Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.)
pp. 94 - 99
ICD2025-56
Implementation and Evaluation of Latency Measurement System for FPGA-based High-speed Ethernet MAC
Yoshito Higa, Junsei Tabata, Mizuki Sakata, Yasunori Osana (Kumamoto Univ.)
pp. 100 - 104
ICD2025-57
A Note on Mitigation of Local Congestion in Gap Channel Routing
Yohei Tomonaga, Masayuki shimoda, Atsushi Takahashi (Science Tokyo)
pp. 105 - 110
ICD2025-58
Implementation and evaluation of loop flattening with power-of-two extension in accelerator design tool
Atsushi Idera, Kenshu Seto (Kumamoto University)
pp. 111 - 116
ICD2025-59
A Low-Power Wireless EEG Transmission System with Hardware-Signal Processing Integration Using Compressed Sensing
-- Outdoor Verification at the Expo Site: Operation with Only Minimal Energy Harvested from Body-Ambient Temperature Differences --
Daisuke Kanemoto, kazane Yoshimoto, Shodai Motomochi, Tetsuya Hirose (UOsaka)
pp. 117 - 122
ICD2025-60
Inference Accuracy Compensation Method for Achieving 10-Year Data Retention in TaOx ReRAM-Based Analog Computation-in-Memory
Yusuke Hirata, Kenshin Yamauchi, Naoko Misawa, Chihiro Matsui, Ken Takeuchi (Univ. Tokyo)
pp. 123 - 126
ICD2025-61
Compensation of duty cycle variation in frequency dividers at low temperatures using Forward Body Bias
Koshi Kitamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture)
pp. 127 - 131
ICD2025-62
Automatic FPGA Design for DNN Inference Processing Using Generative AI Agents
Kenta Naito, Yasutaka Serizawa, Hisanori Matsumoto (Hitachi)
pp. 132 - 136
ICD2025-63
Evaluation of Coarse-Grained Reconfigurable Architectures for Cryptographic Applications
Takuya Kojima (Univ. of Tsukuba), Hisako Ito (UTokyo)
pp. 137 - 142
ICD2025-64
FPGA-Based Accelerator for Hardware-Friendly Fully Quantized Matrix Arithmetic-Only BERT Model
Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki (AIST)
pp. 143 - 148
ICD2025-65
Development of an Automatic Generation Tool for Embedded FPGA-IP for ASICs
Kodai Takeno, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.)
pp. 149 - 154
ICD2025-66
Experimental Study of an Electrical Interconnect Test Method for Interrupt Signal Lines using a Relaxation Oscillator
Yuya Yamahashi, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ)
pp. 155 - 160
ICD2025-67
Experimental evaluation of an arbiter PUF embedded in a delay testable design
Yasuhiro Fujino, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ)
pp. 161 - 166
ICD2025-68
A Proposal for a Test Method Using Self-Monitoring Boundary-Scan to Detect Resistive Open Faults
Shuya Minami, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ)
pp. 167 - 172
ICD2025-69
[Invited Talk]
Solutions for Large Scale Complex Design Challange and Development Efficiency by Artificial Intelligence
Yuya Suzuki (NSGK)
p. 173
ICD2025-70
N/A
Takeru Ota, Tatsuhiko Shirai (Waseda Univ.), Nozomu Togawa (Waseda Univ./Quanmatic)
pp. 174 - 179
ICD2025-71
N/A
Inaba Shinnosuke, Togawa Nozomu (Waseda Univ.)
pp. 180 - 185
ICD2025-72
N/A
Yoshihito Saito, Koki Mita, Nozomu Togawa (Waseda Univ.)
pp. 186 - 191
ICD2025-73
N/A
Raio Aoki, Takeru Ota, Tatsuhiko Shirai, Nozomu Togawa (Waseda Univ.)
pp. 192 - 197
ICD2025-74
Fault-Injected Weight-Adjusting Training for Reliable Memristor-Based Neural Networks.
Md. Sihabul Islam, Taisho Sasada, Michiko Inoue (NAIST)
pp. 198 - 203
ICD2025-75
LLM-Driven Testability Analysis for Gate-Level Circuits
Akitaka Ide, Wang Senling, Hiroshi Kai, Higami Yoshinobu, Hiroshi Takahashi (Ehime Univ)
pp. 204 - 209
ICD2025-76
Study of RS-DICE with Aging Resistance
Keishin Kotake, Kazuteru Namba (Chiba univ.)
pp. 210 - 214
ICD2025-77
N/A
Shu Tomita, Raio Aoki, Shinnosuke Inaba, Masashi Tawada, Nozomu Togawa (Waseda Univ.)
pp. 215 - 220
ICD2025-78
N/A
Ayami Tanaka, Shoma Kaji, Takeru Ota, Yuka Ikegami, Siya Bao, Nozomu Togawa (Waseda Univ.)
pp. 221 - 226
ICD2025-79
Investigation of ReRAM Mapping Techniques for Storing Quantized KV Cache in LLMs
Shota Suzuki, Naoko Misawa, Chihiro Matsui, Ken Takeuchi (The Univ. of Tokyo)
pp. 227 - 232
ICD2025-80
Design and Evaluation of FPGA-based 8-bit Exact Multipliers: Low-Resource and Low-Latency Approaches
Yutaka Narita, Misaki Kida, Shimpei Sato (Shinshu Univ.)
pp. 233 - 238
ICD2025-81
Computation-Reduction Techniques and Optimization Software for Variable-Parallel Reconfigurable Architectures
Yu Inoue, Atsushi Hori, Takao Marukame, Tetsuya Asai (Hokkaido University.), Alexandre Schmid (EPFL), Kota Ando (Hokkaido University.)
pp. 239 - 244
ICD2025-82
Investigation of Streaming Architecture for Extracting Depth Information from Images
Haruka Takahashi, Kota Ando, Takao Marukame, Tetsuya Asai (Hokkaido Univ.)
pp. 245 - 250
ICD2025-83
Element Value Optimization for Buffer in Cryogenic DACs
Kengo Usui, Nobukazu takai (KIT)
pp. 251 - 255
ICD2025-84
Verification of the effectiveness of global sensitivity analysis techniques in automatic design algorithms for analog integrated circuits
Takayoshi Namura, Nobukazu Takai (KIT)
pp. 256 - 260
ICD2025-85
Monte Carlo Tree Search-Based Device Selection for Automated Analog Circuit Design
Yuto Moriguchi, Nobukazu Takai (KIT)
pp. 261 - 266
ICD2025-86
Preliminary Study of Placement and Routing Method for Non-Island-Style eFPGA
Yumi Iseki, Tatsuya Sasaki, Masahiro Iida, Kenshu Seto (Kumamoto Univ.)
pp. 267 - 272
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.