IEICE Technical Report

Online edition: ISSN 2432-6380

Dependable Computing

Workshop Date : 2026-02-17 / Issue Date : 2026-02-10

DC2025-111
(See Japanese page.)
pp. 1 - 6

DC2025-112
(See Japanese page.)
pp. 7 - 12

DC2025-113
Quantitative Evaluation of Inference Accuracy in FPGA-Implemented Binarized Neural Networks via Fault Injection Experiments
Keisuke Kamita, Hiroshi Kai, Wang Senling, Hiroshi Takahashi (Ehime Univ.)
pp. 13 - 18

DC2025-114
A method for detecting hardware Trojans in RTL designs using GIN
Hiroto Totsuka, Masayoshi Yoshimura (Kyoto Sangyo Univ)
pp. 19 - 24

DC2025-115
(See Japanese page.)
pp. 25 - 30

DC2025-116
Experimental analysis of Built-In Self-Test for Stochastic Computing Circuits
Akira Matsumoto, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ)
pp. 31 - 36

DC2025-117
Fault detection probability for uniformly random patterns and its calculation method
Yuya Koizumi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)
pp. 37 - 42

DC2025-118
A Field Test Mechanism Using Adjustable Delay Elements in an Asynchronous Processor
Kenta Hasebe, Satoshi Ohtake (Oita Univ.)
pp. 43 - 48

DC2025-119
An M by One Algorithm to Compact Test Sets with Complete Diagnostic Resolution
Tatsuya Aono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai (Nihon Univ.)
pp. 49 - 54

DC2025-120
On a Test Generation Method for Two-Cycle Gate-Exhaustive Small Delay Faults
Hayata Higano, Akio Kataoka, Tao Sawada, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)
pp. 55 - 60

DC2025-121
(See Japanese page.)
pp. 61 - 64

DC2025-122
A study on countermeasures against degradation of CMOS circuits
Haruka Sakai, Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 65 - 70

DC2025-123
Investigation of the Effect of Output Buffer Insertion on Latch Delay Characteristics
Ryo Saito, Kazuteru Namba (Chiba Univ.)
pp. 71 - 75

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan