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|
| Chair |
|
Tetsuro Endo (Tohoku Univ.) |
| Vice Chair |
|
Yasuo Nara (Fujitsu Semiconductor) |
| Secretary |
|
Yukinori Ono (NTT), Shintaro Nomura (Univ. of Tsukuba) |
| Assistant |
|
Yoshitaka Sasago (Hitachi) |
|
|
|
| Chair |
|
Masahiko Yoshimoto (Kobe Univ.) |
| Vice Chair |
|
Takeshi Yamamura (Fujitsu Labs.) |
| Secretary |
|
Hiroaki Suzuki (Renesas), Toshimasa Matsuoka (Osaka Univ.) |
| Assistant |
|
Ken Takeuchi (Univ. of Tokyo), Osamu Watanabe (Toshiba), Akira Tsuchiya (Kyoto Univ.) |
|
| Conference Date |
Thu, Aug 25, 2011 09:00 - 17:45
Fri, Aug 26, 2011 09:00 - 17:20 |
| Topics |
Low voltage/low power techniques, novel devices, circuits, and applications |
| Conference Place |
Toyama Kenmin-Kaikan |
| Address |
4-18, Shinsougawa, Toyama-Shi, Japan |
| Transportation Guide |
http://kenminkaikan.com/ |
Contact
Person |
Prof. Toshihiro Matsuda
0766-56-7500（Ext502）, 076-432-3111（OnSite） |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Thu, Aug 25 AM
09:00 - 17:45 |
| (1) |
09:00-09:25 |
Study of pattern area reduction with 3 dimensional transistor for logic circuit  SDM2011-71 ICD2011-39 |
Takahiro Kodama, Shigeyoshi Watanabe (SIT), Yu Hiroshima (Oi Electric) |
| (2) |
09:25-09:50 |
Study of pattern area reduction for standard cell with planar and SGT transistor SDM2011-72 ICD2011-40 |
Takahiro Kodama, Shigeyoshi Watanabe (SIT) |
| (3) |
09:50-10:15 |
Study of pattern area for reconfigurable logic circuit with DG/CNT transistor SDM2011-73 ICD2011-41 |
Takamichi Hayashi, Shigeyoshi Watanabe (SIT) |
| |
10:15-10:25 |
Break ( 10 min. ) |
| (4) |
10:25-10:50 |
Power-Performance Estimation of Datta-Das Spin Transistor SDM2011-74 ICD2011-42 |
Yoshiyuki Kondo, Shigeru Kawanaka, Kanna Adachi (Toshiba) |
| (5) |
10:50-11:15 |
Plasma Doping and Laser Spike Annealing Technique for Steep SDE Formation in nano-scale MOSFET SDM2011-75 ICD2011-43 |
Emiko Sugizaki, Toshitaka Miyata, Yasunori Oshima, Akira Hokazono, Kanna Adachi, Kiyotaka Miyano, Hideji Tsujii, Shigeru Kawanaka, Satoshi Inaba, Takaharu Itani, Toshihiko Iinuma, Yoshiaki Toyoshima (Toshiba) |
| (6) |
11:15-12:00 |
[Invited Talk]
Ferroelectric Random Access Memory
-- Fundamentals, recent advancements and future -- SDM2011-76 ICD2011-44 |
Shoichiro Kawashima (FSL) |
| |
12:00-12:50 |
Lunch ( 50 min. ) |
| (7) |
12:50-13:35 |
[Invited Talk]
Sub-nanowatt Circuit Techniques Enabling Wireless-sensor-node Operation with an Energy Harvester SDM2011-77 ICD2011-45 |
Mamoru Ugajin, Toshishige Shimamura, Hiroki Morimura, Shin'ichiro Mutoh, Mitsuru Harada (NTT) |
| (8) |
13:35-14:20 |
[Invited Talk]
A Wireless Self-powered Sensor with Ambient Energy Sources SDM2011-78 ICD2011-46 |
Takakuni Douseki (Ritsumeikan Univ.) |
| |
14:20-14:30 |
Break ( 10 min. ) |
| (9) |
14:30-14:55 |
A Low Power 90-nm CMOS Motion Estimation Processor Array Implementing Stick-shaped Search Window (SSW) Block Matching Algorithm SDM2011-79 ICD2011-47 |
Tadayoshi Enomoto (Chuo Univ.) |
| (10) |
14:55-15:20 |
Novel power reduction technique for ReRAM with the automatic evasion circuit of the wasteful overwrite SDM2011-80 ICD2011-48 |
Takaya Handa, Kazuya Nakayama, Akio Kitagawa, Junichi Akita (Kanazawa Univ.) |
| (11) |
15:20-16:05 |
[Invited Talk]
Applications/Market Trends of Energy Harvesting SDM2011-81 ICD2011-49 |
Keiji Takeuchi (NTT Data Institute of Management Consulting) |
| |
16:05-16:15 |
Break ( 10 min. ) |
| (12) |
16:15-17:45 |
[Panel Discussion]
Ultralow-power technologies for energy harvesting sensor network systems SDM2011-82 ICD2011-50 |
Keiji Takeuchi (NTT Data BR), Mamoru Ugajin (NTT), Syouichirou Kawasaki (Fujitsu), Takakuni Douseki (Ritsu), Makoto Takamiya (U-Tokyo), Jiro Ida, Yuichi Kado (KIT) |
Fri, Aug 26 AM
09:00 - 17:20 |
| (13) |
09:00-09:25 |
Evaluation of Variability in High-k/Metal-Gate MOSFET using Takeuchi Plot SDM2011-83 ICD2011-51 |
Tomoko Mizutani, Anil Kumar (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) |
| (14) |
09:25-09:50 |
Statistical Analysis of DIBL and Current-Onset Voltage (COV) Variability in Scaled MOSFETs SDM2011-84 ICD2011-52 |
Anil Kumar, Tomoko Mizutani (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) |
| (15) |
09:50-10:15 |
Phase-change memory driven by poly-Si MOS transistor with low cost and high-programming throughput SDM2011-85 ICD2011-53 |
Yoshitaka Sasago, Masaharu Kinoshita, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Kenzo Kurotsuchi, Seiichi Morita, Toshikazu Takahashi, Takashi Takahama, Tadao Morimoto, Toshiyuki Mine, Akio Shima, Takashi Kobayashi (Hitachi) |
| |
10:15-10:25 |
Break ( 10 min. ) |
| (16) |
10:25-11:10 |
[Invited Talk]
Status and Prospect of Ultra Low Power Logic Devices SDM2011-86 ICD2011-54 |
Jiro Ida (KIT) |
| (17) |
11:10-11:55 |
[Invited Talk]
Technology Trends in Low Power Digital Circuits SDM2011-87 ICD2011-55 |
Masaya Sumita (Panasonic) |
| |
11:55-12:55 |
Lunch ( 60 min. ) |
| (18) |
12:55-13:40 |
[Invited Talk]
0.5V Extremely Low Power Circuits for Wireless Sensor Nodes with Energy Harvesting SDM2011-88 ICD2011-56 |
Makoto Takamiya, Koichi Ishida, Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) |
| (19) |
13:40-14:05 |
Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array SDM2011-89 ICD2011-57 |
Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi) |
| (20) |
14:05-14:30 |
Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays SDM2011-90 ICD2011-58 |
Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi) |
| |
14:30-14:40 |
Break ( 10 min. ) |
| (21) |
14:40-15:05 |
Dependable SRAM with Enhanced Read-/Write-Margins by Fine-Grained Assist Bias Control for Low-Voltage Operation SDM2011-91 ICD2011-59 |
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto (Renesas) |
| (22) |
15:05-15:30 |
A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue SDM2011-92 ICD2011-60 |
Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) |
| (23) |
15:30-15:55 |
A Dynamic body-biased SRAM with Asymmetric Halo Implant MOSFETs SDM2011-93 ICD2011-61 |
Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Koji Maekawa, Motoshige Igarashi, Koji Nii (Renesas) |
| |
15:55-16:05 |
Break ( 10 min. ) |
| (24) |
16:05-16:30 |
Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection SDM2011-94 ICD2011-62 |
Kentaro Honda, Katsuyuki Ikeuchi (Univ. of Tokyo), Masahiro Nomura (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) |
| (25) |
16:30-16:55 |
Energy Efficiency Increase of Integer Unit Enabled by Contention-less Flip-Flops (CLFF) and Separated Supply Voltage between Flip-Flops and Combinational Logics SDM2011-95 ICD2011-63 |
Hiroshi Fuketa (Univ. of Tokyo), Koji Hirairi (STARC), Tadashi Yasufuku, Makoto Takamiya (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) |
| (26) |
16:55-17:20 |
Optimization of the low voltage operation Circuits for the Self-synchronous system SDM2011-96 ICD2011-64 |
Ayumi Kamitani, Makoto Ikeda (Tokyo Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Invited Talk | Each speech will have 40 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| SDM |
Technical Committee on Silicon Device and Materials (SDM) [Latest Schedule]
|
| Contact Address |
Yukinori Ono(NTT)
Tel 046-240-2641 Fax 046-240-4317
E- : o         |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Minoru Fujishima (The University of Tokyo)
TEL 03-5841-7425,FAX 03-5841-8575
E-:  eetu-  |
Last modified: 2011-08-11 19:31:35
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