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Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Kota Nakajima (Fujitsu Lab.)
Vice Chair Yasushi Inoguchi (JAIST), Tomoaki Tsumura (Nagoya Inst. of Tech.)
Secretary Ryohei Kobayashi (Univ. of Tsukuba), Shugo Ogawa (Hitachi)
Assistant Ryuichi Sakamoto (Tokyo Inst. of Tech.), Takumi Honda (Fujitsu)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Tatsuhiro Tsuchiya (Osaka Univ.)
Vice Chair Toshinori Hosokawa (Nihon Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yoshiki Yamaguchi (Tsukuba Univ.)
Vice Chair Yasushi Inoguchi (JAIST), Tomonori Izumi (Ritsumeikan Univ.)
Secretary Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.)
Assistant Yukitaka Takemura (INTEL), Yasunori Osana (Kumamoto Univ.)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Tomoaki Tsumura (Nagoya Inst. of Tech.)
Secretary Hiroe Iwasaki, Takayuki Onishi (NTT), Yasushi Kurihara (Fujitsu), Hayato Yamaki (UEC)

Conference Date Mon, Jun 10, 2024 13:45 - 18:00
Tue, Jun 11, 2024 09:30 - 20:00
Wed, Jun 12, 2024 09:30 - 12:15
Topics System Architecture, Computer Systems, Dependable Computing, Reconfigurable System, etc. 
Conference Place  
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on CPSY, DC, RECONF.

Mon, Jun 10 PM 
13:45 - 15:00
(1)
RECONF		 13:45-14:10 FPGA Implementation of a One-Instruction-Set Computer and Evaluation of Power Consumption CPSY2024-1 DC2024-1 RECONF2024-1 Ariya Ochirtsogt, Kenji Kanazawa (Tsukuba Univ.)
(2) 14:10-14:35  
(3) 14:35-15:00  
  15:00-15:15 Break ( 15 min. )
Mon, Jun 10 PM 
15:15 - 16:05
(4)
CPSY		 15:15-15:40 Study of control flow decoupling for controller design exploration in CGRA CPSY2024-2 DC2024-2 RECONF2024-2 Hisako Ito, Takuya Kojima, Hideki Takase, Hiroshi Namkamura (Univ. of Tokyo)
(5) 15:40-16:05  
  16:05-16:20 Break ( 15 min. )
Mon, Jun 10 PM 
16:20 - 18:00
(6)
CPSY		 16:20-16:45 Rapid Inter-Thread Communication Using Message Passing Unit in RISC-V SMT Processor CPSY2024-3 DC2024-3 RECONF2024-3 Go Akamatsu, Shogo Takata, Tomoaki Tanaka, Hironori Nakajo (TUAT)
(7)
RECONF		 16:45-17:10 CPSY2024-4 DC2024-4 RECONF2024-4 Akinobu Tomori, Yasunori Osana (Kumamoto Univ.)
(8)
RECONF		 17:10-17:35 Preliminary Report on an FPGA-based Prototype of a Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking CPSY2024-5 DC2024-5 RECONF2024-5 Akram Ben Ahmed, Takahiro Hirofuchi, Takaaki Fukai (AIST)
(9) 17:35-18:00  
  18:00-19:00 Break ( 60 min. )
  - Social Dinner
Tue, Jun 11 AM 
09:30 - 10:30
(10)
CPSY		 09:30-09:55 CPSY2024-6 DC2024-6 RECONF2024-6 Yasuhiko Nakashima (NAIST)
(11)
RECONF		 09:55-10:05 A preliminary evaluation of CNNs' performance of meteor detection using training data by generative AI towards FPGA implementation CPSY2024-7 DC2024-7 RECONF2024-7 Zheng Yuping, Kenji Kanazawa (Univ. Tsukuba)
(12) 10:05-10:30  
  10:30-10:45 Break ( 15 min. )
Tue, Jun 11 PM 
10:45 - 11:45
(13)
DC		 10:45-11:10 Fault classification and prediction of AI accelerators based on activation maximization CPSY2024-8 DC2024-8 RECONF2024-8 Ma Shanmou, Kazuteru Namba (Chiba Univ.)
(14)
DC		 11:10-11:35 A LBIST Method for Detecting Fault Locations in AI Accelerators CPSY2024-9 DC2024-9 RECONF2024-9 Zhang Jiaxi, Namba Kazuteru (Chiba Univ)
(15)
RECONF		 11:35-11:45 Quantitative quality control efforts in FPGA development. Kenji Okazaki, Hiroyuki Uchida (FUJIFILM Software Co., Ltd.)
  11:45-13:15 Lunch Break ( 90 min. )
Tue, Jun 11 PM 
13:15 - 14:30
(16)
DC		 13:15-13:40 Burst Length Optimization in MLC PCM using Encoding and Merge Sort CPSY2024-10 DC2024-10 RECONF2024-10 Jin Lei, Kazuteru Namba (Chiba Univ.)
(17)
RECONF		 13:40-14:05 CPSY2024-11 DC2024-11 RECONF2024-11
(18) 14:05-14:30  
  14:30-14:45 Break ( 15 min. )
Tue, Jun 11 PM 
14:45 - 16:00
(19) 14:45-15:10  
(20)
RECONF		 15:10-15:35 A Framework for Efficient Evaluation of Side-Channel Attack Resistance
-- A Case Study of HLS-designed AES -- CPSY2024-12 DC2024-12 RECONF2024-12		 Takuya Kojima (UTokyo)
(21) 15:35-16:00  
  16:00-16:15 Break ( 15 min. )
Tue, Jun 11 PM 
16:15 - 17:30
(22) 16:15-16:40  
(23) 16:40-17:05  
(24) 17:05-17:30  
  17:30-19:00 Break ( 90 min. )
Tue, Jun 11 PM 
19:00 - 20:00
(25)
RECONF		 19:00-19:00 An Example of System Design Using Python (LiteSATA) (Temporary) Ryohei Niwase (Univ. Tsukuba)
(26)
RECONF		 19:00-19:00 On the Design and Implementation of Point Cloud-Based Applications with Pynq and High-Level Synthesis CPSY2024-13 DC2024-13 RECONF2024-13 Keisuke Sugiura (Keio Univ.)
(27)
RECONF		 19:00-19:00 An Example of System Design Using Python (LiteX/MigenDSL) (Temporary) Yuji Yamada (Tokyo Tech)
(28) 19:00-20:00  
Wed, Jun 12 AM 
09:30 - 10:45
(29)
RECONF		 09:30-09:55 Exploration and Simulation of FPGA Utilizing 3D-SRAM CPSY2024-14 DC2024-14 RECONF2024-14 Ryo Takahashi (Tokyo Tech), Hiroki Nakahara (Tohoku Univ.)
(30)
RECONF		 09:55-10:20 Memory-centric CGRA with variable parallelism for neural networks CPSY2024-15 DC2024-15 RECONF2024-15 Atsushi Hori, Fumiya Arai, Tetsuya Asai, Kota Ando (Hokkaido Univ.)
(31) 10:20-10:45  
  10:45-11:00 Break ( 15 min. )
Wed, Jun 12 PM 
11:00 - 12:15
(32) 11:00-11:25  
(33) 11:25-11:50  
(34) 11:50-12:15  

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address CPSY WEB
https://www.ieice.org/~cpsy/ 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masayuki Arai (College of Industrial Technology, Nihon Univ.)
E--mail: ain-u 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Chair: Yoshiki Yamaguchi (Tsukuba Univ.) 
Announcement RECONF website
http://www.ieice.org/~reconf/
RECONF slack
https://join.slack.com/t/reconfworkspace/shared_invite/zt-v3qeynk3-RsInu4wdjqU2t_ysqWvagg
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  


Last modified: 2024-05-22 13:22:01


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