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| Chair |
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Hiroshi Takahashi (Ehime Univ.) |
| Vice Chair |
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Tatsuhiro Tsuchiya (Osaka Univ.) |
| Secretary |
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Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.) |
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| Conference Date |
Fri, Feb 5, 2021 10:30 - 16:45 |
| Topics |
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| Conference Place |
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Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on DC. |
Fri, Feb 5 AM
10:30 - 11:20 |
| (1) |
10:30-10:55 |
A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA  DC2020-69 |
Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.) |
| (2) |
10:55-11:20 |
Hardware Trojan Detection by Learning Power Side Channel Signals Considering Random Process Variation DC2020-70 |
Michiko Inoue, Riaz-Ul-Haque Mian (NAIST) |
| |
11:20-11:35 |
Break ( 15 min. ) |
Fri, Feb 5 AM
11:35 - 12:50 |
| (3) |
11:35-12:00 |
A Novel High Performance Scan-Test-Aware Hardened Latch Design DC2020-71 |
Ruijun Ma, Stefan Holst, Xiaoqing Wen (KIT), Aibin Yan (AHU), Hui Xu (AUST) |
| (4) |
12:00-12:25 |
Locating High Power Consuming Area in Logic parts Caused by Memory Size and Shapes DC2020-72 |
Daiki Takafuji, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) |
| (5) |
12:25-12:50 |
DC2020-73 |
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12:50-14:00 |
Break ( 70 min. ) |
Fri, Feb 5 PM
14:00 - 15:15 |
| (6) |
14:00-14:25 |
Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements DC2020-74 |
Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) |
| (7) |
14:25-14:50 |
Fault Coverage Estimation Method in Multi-Cycle Testing DC2020-75 |
Norihiro Nakaoka, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas Electronics Corp.) |
| (8) |
14:50-15:15 |
A Test Generation Method Using Information of Easily Testable Functional Time Expansion Model DC2020-76 |
Kenta Nakamura, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Fri, Feb 5 PM
15:30 - 16:45 |
| (9) |
15:30-15:55 |
A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level DC2020-77 |
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
| (10) |
15:55-16:20 |
DC2020-78 |
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| (11) |
16:20-16:45 |
DC2020-79 |
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| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
Masayuki Arai (College of Industrial Technology, Nihon Univ.)
E- : a i        n-u |
Last modified: 2021-02-04 12:03:34
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