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| Chair |
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Yuichi Sakurai (Hitachi) |
| Vice Chair |
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Hiroyuki Tomiyama (Ritsumeikan Univ.) |
| Secretary |
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Yukihiro Sasagawa (Socionext), Kenshu Seto (Kumamot Univ.) |
| Assistant |
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Takuma Nishimoto (Hitachi), Ami TANAKA (Ritsumeikan Univ.), Masayuki Odagawa (Cadence Design Systems, Japan) |
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| Chair |
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Yoshiki Yamaguchi (Univ. of Tsukuba / Kumamoto Univ.) |
| Vice Chair |
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Yasushi Inoguchi (JAIST), Tomonori Izumi (Ritsumeikan Univ.) |
| Secretary |
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Yutaka Yamada (Toshiba), Yukinori Sato (Toyohashi Univ. of Tech.) |
| Assistant |
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Yukitaka Takemura (INTEL), Yasunori Osana (Kumamoto Univ.) |
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| Conference Date |
Thu, Jan 16, 2025 09:00 - 17:25
Fri, Jan 17, 2025 09:00 - 17:30 |
| Topics |
FPGA Applications, etc. |
| Conference Place |
KIOXIA Corporation Yokohama Technology Campus Flagship Bldg. 2F（Event space ） |
| Address |
2-5-1 Kasama, Sakae-ku, Yokohama-shi, Kanagawa, 247-8585 Japan. |
| Transportation Guide |
Take the Kasama Exit of Ofuna Station and cross the street at the traffic light. Walk on the sidewalk along the GRAND SHIP mall. The entrance to KIOXIA is at the back of the bus terminal.
https://www.ieice.org/~vld/2024/KIOXIA_AccessMap.pdf |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, RECONF. |
| Due for Registration |
Please proceed the payment of registration fee by 3 days before the workshop date. The meeting URL will be sent from one of the secretaries of the committee via e-mail, just before the workshop date. |
| Registration for Online |
If you will join the workshop/conference held in online/hybrid style, please make your registration here, for getting the meeting ID and pass code. (Japanese page) |
Thu, Jan 16 AM
09:00 - 10:15 |
| (1) |
09:00-09:25 |
Consideration of Logic Gate Structure Using Vertical Nanowire Transistors |
Genta Nakamura (Kyushu Univ), Katsuhiro Tomioka (Hokkaido Univ), Koji Inoue (Kyushu Univ) |
| (2) |
09:25-09:50 |
Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning |
Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi (Kyoto Univ.), Kozo Takeuchi (JAXA), Masanori Hashimoto (Kyoto Univ.) |
| (3) |
09:50-10:15 |
Implementation of an Error Correcting Decoder for Surface Code Using Greedy Algorithm on ASIC by RTL and Behavioral Synthesis |
Ren Aoyama (KIT), Junichiro Kaodomoto (UTokyo), Kazutoshi Kobayashi (KIT) |
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10:15-10:30 |
Break ( 15 min. ) |
Thu, Jan 16 PM
10:30 - 11:45 |
| (4) |
10:30-10:55 |
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| (5) |
10:55-11:20 |
An FPGA Implementation of Object Tracking System using Center of Mass Computation with Integral Images |
Yusuke Hara, Shinji Fukuma (Fukui Univ) |
| (6) |
11:20-11:45 |
Stabilization Techniques for Online Computation-Oriented Linear Equation Solvers Targeting FPGA Implementation |
Yuma Omoto, Yuya Shuto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) |
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11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Jan 16 PM
13:00 - 14:00 |
| (7) |
13:00-14:00 |
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14:00-14:15 |
Break ( 15 min. ) |
Thu, Jan 16 PM
14:15 - 15:55 |
| (8) |
14:15-14:40 |
Global Routing for CBA-based 3D Flash Memory |
Masayuki Shimoda, Atsushi Takahashi (Science Tokyo), Kosuke Yanagidaira, Mikiko Hirai (KIOXIA), Toshikazu Watanabe, Toshimitsu Iwasawa (KIOXIA Systems), Chikaaki Kodama (KIOXIA) |
| (9) |
14:40-15:05 |
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| (10) |
15:05-15:30 |
Efficient FPGA Implementation of Compressor Trees Based on Generalized Parallel Counter Chains |
Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.) |
| (11) |
15:30-15:55 |
Hardware Design Using Python for Full Hardware Implementation of RTOS-Based Systems |
Hikaru Shiga, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) |
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15:55-16:10 |
Break ( 15 min. ) |
Thu, Jan 16 PM
16:10 - 17:25 |
| (12) |
16:10-16:35 |
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| (13) |
16:35-17:00 |
Preliminary evaluation of FPGA-based syndrome subgraph decoder for quantum error correction |
Prasoon Ambalathankandy, Werner Florian Samayoa, Jan Erik Reinhard Wichmann (RIKEN RCCS), Yukito Taguchi, Yuichiro Shibata (Nagasaki Univ), Kentaro Sano (RIKEN RCCS) |
| (14) |
17:00-17:25 |
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Fri, Jan 17 AM
09:00 - 10:15 |
| (15) |
09:00-09:25 |
A design hackathon aimed at sparking interest in semiconductors with an AI application |
Takao Goto, Mizuho Nitami, Hideharu Amano, Atsutake Kosuge, Yuki Mitarai, Jiawei Yu, Yuxuan PAN, Makoto Ikeda (The Univ. of Tokyo) |
| (16) |
09:25-09:50 |
"Shochiku-V": CPU of "LAXER-SoC" for industrial edge devices |
Daiki Matsunaga, Shozo Takeoka (AXE) |
| (17) |
09:50-10:15 |
Comparison of FPGA and OpenLane Implementations of a Single Instruction Set Computer |
Ochirsogt Ariya (Tsukuba Univ./AIST), Yohei Hori, Toshihiro Katashita, Masakazu Hioki (AIST), Kenji Kanazawa (Tsukuba Univ.) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Fri, Jan 17 PM
10:30 - 11:45 |
| (18) |
10:30-10:55 |
Investigation of patch-based neural networks for super-resolution hardware |
Junya Kibushi, Cong-Kha Pham (UEC) |
| (19) |
10:55-11:20 |
Design of Convolutional Neural Network Hardware with Systolic Array |
Shu Oguro, Cong-Kha Pham (UEC) |
| (20) |
11:20-11:45 |
Configuration of a CNN accelerator using Winogard algorithm |
Kota Saito, Cong-Kha Pham (UEC) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Fri, Jan 17 PM
13:00 - 13:40 |
| (21) |
13:00-13:40 |
[Invited Talk]
Challenge to reproduce CPU processing by reading/writing flash memory |
Masahiro Kusaka |
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13:40-13:55 |
Break ( 15 min. ) |
Fri, Jan 17 PM
13:55 - 15:35 |
| (22) |
13:55-14:20 |
Introduction and Evaluation of a Programmable Buffer for Stencil Computation on RIKEN CGRA |
Takumi Okada, Yasunori Osana, Masahiro Iida (Kumamoto Univ.), Boma Adhi, Kentaro Sano (R-CCS), Omar Ragheb, Jason Anderson (UofT) |
| (23) |
14:20-14:45 |
Emulation Environment for Reconfigurable Virtual Accelerator (ReVA) with QEMU |
Kaoru Kayukawa, Shunya Kawai, Kazuki Yaguchi (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo, LCC.), Hironori Nakajo (TUAT) |
| (24) |
14:45-15:10 |
Development of Self-Calibration Hardware Interface for a Peripheral on Super General Purpose SoC |
Hibiki Shinozaki, Akira Yamawaki (KIT) |
| (25) |
15:10-15:35 |
Proposal and evaluation of Heterostructure Clusters Using PAE Cells for eFPGA IP |
Tatsuya Sasaki, Ryo Iwasaki, Kensyu Seto, Masahiro Iida (Kumamoto Univ.) |
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15:35-15:50 |
Break ( 15 min. ) |
Fri, Jan 17 PM
15:50 - 17:30 |
| (26) |
15:50-16:15 |
A Graph Neural Network based approach for FPGA routing |
Kazuki Tokuishi, Masato Kiyama, Motoki Amagasaki, Kenshu Seto (Kumamoto Univ.) |
| (27) |
16:15-16:40 |
An FPGA Implementation Using Non-binary LDPC Code for Continuous-Variable Quantum Key Distribution |
Kaijie Wei (Keio Univ.), Devanshu Garg (Blueqat Inc.), Ryutaro Nagai (SCSK Corp.), Takao Tomono (Keio Univ.), Hideharu Amano (U.Tokyo) |
| (28) |
16:40-17:05 |
Clock distribution method on FPGAs without any dedicated clock tree |
Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
| (29) |
17:05-17:30 |
Radiation degradation of the configuration circuit on a dynamic optically reconfigurable gate array |
Seiji Ohashi, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
Last modified: 2024-11-20 00:20:19
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