IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Circuits and Systems (CAS) [schedule] [select]
Chair Norihiko Shinomiya (Soka Univ.)
Vice Chair Shinji Shimoda (Sony Semiconductor Solutions)
Secretary Daisuke Kasamatsu (Soka Univ.), Yasuhide Takase (Murata Manufacturing)
Assistant Nao Ito (NIT, Toyama college), Shunsuke Koshita (Hachinohe Inst. of Tech.), Hiroto Suzuki (Renesas Electronics)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Yuichi Sakurai (Hitachi)
Vice Chair Hiroyuki Tomiyama (Ritsumeikan Univ.)
Secretary Yukihiro Sasagawa (Socionext), Kenshu Seto (Kumamot Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Signal Processing (SIP) [schedule] [select]
Chair Koichi Ichige (Yokohama National Univ.)
Vice Chair Akira Tanaka (Hokkaido Univ.), Kiyoshi Nishikawa (okyo Metropolitan Univ.)
Secretary Shoko Imaizumi (Chiba Univ.), Taizo Suzuki (Univ. of Tsukubaba)
Assistant Masanari Nakamura (Hokkaido Univ.), Sayaka Shiota (Tokyo Metropolitan Univ.)

Technical Committee on Mathematical Systems Science and its Applications (MSS) [schedule] [select]
Chair Shingo Yamaguchi (Yamaguchi Univ.)
Vice Chair Toshiyuki Miyamoto (Osaka Inst. of Tech.)
Secretary Naoki Hayashi (Osaka Univ.), Jianquan Liui (NEC)
Assistant Masato Shirai (Shimane Univ.)

Conference Date Thu, Jul 18, 2024 09:30 - 16:30
Fri, Jul 19, 2024 09:30 - 16:30
Topics  
Conference Place  
Sponsors This conference is co-sponsored by Hirosaki University and IEEE Signal Processing Society Tokyo Joint Chapter. This conference is technical co-sponsored by IEEE Circuits and Systems Society Japan Chapter(IEEE CASS JC), IEEE Signal Processing Society Tokyo Joint Chapter and APSIPA Japan Chapter.
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, CAS, SIP, MSS.

Thu, Jul 18 AM 
09:30 - 11:35
(1) 09:30-09:55 Study of instantaneous frequency estimation using finite order 2-D Hilbert transformer CAS2024-1 VLD2024-1 SIP2024-18 MSS2024-1 Yuka Shiraishi, Jun Obara (TUS), Yasunori Sugita (NUT), Naoyuki Aikawa (TUS)
(2) 09:55-10:20 Fast Processing Methods for Generalized Gaussian Functions CAS2024-2 VLD2024-2 SIP2024-19 MSS2024-2 Hirokazu Kamei, Soichiro Honda, Kohei Hayashi, Norishige Fukushima (NITech)
(3) 10:20-10:45 Image Quality Assessment for Detail Enhancement by Synthetic Image Normalization CAS2024-3 VLD2024-3 SIP2024-20 MSS2024-3 Soichiro Honda, HiroKazu Kamei, Kohei Hayashi, Norishige Fukushima (NITech)
(4) 10:45-11:10 A fine-tuning method using encrypted pre-trained model for Vision Transformer considering privacy protection CAS2024-4 VLD2024-4 SIP2024-21 MSS2024-4 Kouki Horio, Kiyoshi Nishikawa, Hitoshi Kiya (TMU)
(5) 11:10-11:35 A method for phase retrieval from STFT magnitude based on the Taylor series expansion of a modified Bargmann transform CAS2024-5 VLD2024-5 SIP2024-22 MSS2024-5 Kazuki Nishino, Takaaki Nara (UTokyo)
  11:35-13:00 Break ( 85 min. )
Thu, Jul 18 PM 
13:00 - 13:50
(6) 13:00-13:25 Analysis of Malicious Botnets and Disinfection by White-Hat Worms Using Mirai Source Code CAS2024-6 VLD2024-6 SIP2024-23 MSS2024-6 Yudai Yamamoto, Aoi Fukushima, Shingo Yamaguchi (Yamaguchi Univ.)
(7) 13:25-13:50 Proposal for an Immune Mechanism in Botnet Defense System CAS2024-7 VLD2024-7 SIP2024-24 MSS2024-7 Shingo Yamaguchi (Yamaguchi Univ.)
  13:50-14:00 Break ( 10 min. )
Thu, Jul 18 PM 
14:00 - 16:30
(8) 14:00-14:25 Measurement of Leakage based Strong PUF Operating at Ultra Low Voltage Using a Leakage Control Approach CAS2024-8 VLD2024-8 SIP2024-25 MSS2024-8 Shunkichi Hata, Kimiyoshi Usami (SIT)
(9) 14:25-14:50 CAS2024-9 VLD2024-9 SIP2024-26 MSS2024-9
(10) 14:50-15:15 NA CAS2024-10 VLD2024-10 SIP2024-27 MSS2024-10 Hibiki Nakanishi (Waseda Univ.), Kento Hasegawa, Seira Hidano, Kazuhide Fukushima (KDDI Research, Inc.), Kazuo Hashimoto, Nozomu Togawa (Waseda Univ.)
(11) 15:15-15:40 Evaluation of BSIM4 at cryogenic temperature using 65nm bulk transistor CAS2024-11 VLD2024-11 SIP2024-28 MSS2024-11 Shin Taniguchi, Michihiro Shintani (KIT)
(12) 15:40-16:05 CAS2024-12 VLD2024-12 SIP2024-29 MSS2024-12
(13) 16:05-16:30 CAS2024-13 VLD2024-13 SIP2024-30 MSS2024-13
Fri, Jul 19 AM 
09:30 - 11:35
(14) 09:30-09:55 Effect of Multiple Pedestrian Information on Machine Learning Indoor Location Estimation CAS2024-14 VLD2024-14 SIP2024-31 MSS2024-14 Nao Ito, Jin Kitsukawa, Kazuya Unjo (NIT, Toyama)
(15) 09:55-10:20 Design of LTCC-based Balanced BPF with Coupled-line Resonators and Ring Resonators CAS2024-15 VLD2024-15 SIP2024-32 MSS2024-15 Tatsuyoshi Tanii, Koji Wada, Hiroki Matsuura (UEC)
(16) 10:20-10:45 On Preparations of proofs of the existence of MMOs
-- Considerations from Urabe's Theorems, Piecewise Linear Models, and a Krawczyk Operator for Function Strips --
CAS2024-16 VLD2024-16 SIP2024-33 MSS2024-16
Hideaki Okazaki, Naohiko Inaba (SIT)
(17) 10:45-11:10 Estimation of Blood Components in Castle Using Near-Infrared Spectroscopy CAS2024-17 VLD2024-17 SIP2024-34 MSS2024-17 Marika Takeshima (TUS), Takahiro Natori (TU), Yuka Kawatus, Hisashi Nabenishi (KU), Naoyuki Aikawa (TUS)
(18) 11:10-11:35 The impact of gaming in negawatt trading on the profits of retail electricity producers CAS2024-18 VLD2024-18 SIP2024-35 MSS2024-18 Takashi Yashiki, Norihiko Shinomiya (Soka Univ.)
  11:35-13:25 Break ( 110 min. )
Fri, Jul 19 PM 
13:25 - 14:40
(19) 13:25-13:50 A Prototype of 21 GHz Wideband Bandpass Filter using a Stub-Loaded Resonator and T-shape Stubs CAS2024-20 VLD2024-20 SIP2024-37 MSS2024-20 Hiroki Matsuura, Sho Kasai, Koji Wada (UEC)
(20) 13:50-14:15 An Examination of the Relationship between the Two-Stage Chebyshev Transmission Line Matching Circuit and the LC Matching Circuit CAS2024-21 VLD2024-21 SIP2024-38 MSS2024-21 Satoshi Tanaka, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.)
(21) 14:15-14:40 Operable Time Evaluation of FPGA-based Sensor Node with Capacitor Power Supply Varying Basic Circuit Resources CAS2024-22 VLD2024-22 SIP2024-39 MSS2024-22 Itsuki Fukumitsu, Akira Yamawaki (Kyutech)
  14:40-14:50 Break ( 10 min. )
Fri, Jul 19 PM 
14:50 - 16:30
(22) 14:50-15:15 CAS2024-23 VLD2024-23 SIP2024-40 MSS2024-23
(23) 15:15-15:40 CAS2024-24 VLD2024-24 SIP2024-41 MSS2024-24
(24) 15:40-16:05 A Routing Method for 2-Layer Comb-shaped Bottleneck Routing Problem CAS2024-25 VLD2024-25 SIP2024-42 MSS2024-25 Ryo Takata, Kunihiro Fujiyoshi (TUAT)
(25) 16:05-16:30 CAS2024-26 VLD2024-26 SIP2024-43 MSS2024-26

Other published manuscript(s)
An attempt to analyze time series data of convergence motion during 3D-maze video viewing (without presentation) CAS2024-19 VLD2024-19 SIP2024-36 MSS2024-19 Yoshinobu Maeda (Niigata Univ.), Masako Ishii (NUHW), Akira Tsukada (NIT, Toyama College)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CAS Technical Committee on Circuits and Systems (CAS)   [Latest Schedule]
Contact Address CAS administrator Group
E--mail: cas-adn 
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yukihiro Sasagawa (Socionext)
E--mail: vld-n24 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
SIP Technical Committee on Signal Processing (SIP)   [Latest Schedule]
Contact Address IEICE Technical Group on Signal Processing
Email: sip-n 
MSS Technical Committee on Mathematical Systems Science and its Applications (MSS)   [Latest Schedule]
Contact Address Masato Shirai (Shimane University)
E--mail: icis-u 


Last modified: 2024-07-16 19:13:07


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to CAS Schedule Page]   /   [Return to VLD Schedule Page]   /   [Return to SIP Schedule Page]   /   [Return to MSS Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan