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Technical Committee on Dependable Computing (DC) (Searched in: 2020)
Search Results: Keywords 'from:2021-02-05 to:2021-02-05'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2021-02-05 10:30 |
Online | Online | A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.)  DC2020-69 |
FPGAs are integrated circuits that can be implemented arbitrary logic functions. In FPGAs, it is important to measure pr... [more] | DC2020-69 pp.1-6 |
| DC | 2021-02-05 10:55 |
Online | Online | Hardware Trojan Detection by Learning Power Side Channel Signals Considering Random Process Variation Michiko Inoue, Riaz-Ul-Haque Mian (NAIST) DC2020-70 |
Due to the globalization and complexity of the supply chain, there is a growing concern about the insertion of hardware ... [more] | DC2020-70 pp.7-11 |
| DC | 2021-02-05 11:35 |
Online | Online | A Novel High Performance Scan-Test-Aware Hardened Latch Design Ruijun Ma, Stefan Holst, Xiaoqing Wen (KIT), Aibin Yan (AHU), Hui Xu (AUST) DC2020-71 |
As modern technology nodes become more and more susceptible to soft-errors, many radiation hardened latch designs have b... [more] | DC2020-71 pp.12-17 |
| DC | 2021-02-05 12:00 |
Online | Online | Locating High Power Consuming Area in Logic parts Caused by Memory Size and Shapes Daiki Takafuji, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2020-72 |
[more] | DC2020-72 pp.18-23 |
| DC | 2021-02-05 12:25 |
Online | Online | DC2020-73 |
[more] | DC2020-73 pp.24-29 |
| DC | 2021-02-05 14:00 |
Online | Online | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| DC | 2021-02-05 14:25 |
Online | Online | Fault Coverage Estimation Method in Multi-Cycle Testing Norihiro Nakaoka, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas Electronics Corp.) DC2020-75 |
[more] | DC2020-75 pp.36-41 |
| DC | 2021-02-05 14:50 |
Online | Online | A Test Generation Method Using Information of Easily Testable Functional Time Expansion Model Kenta Nakamura, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.) DC2020-76 |
[more] | DC2020-76 pp.42-47 |
| DC | 2021-02-05 15:30 |
Online | Online | A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2020-77 |
A field testing that monitors the values of circuit outputs and internal signal lines during function mode is used as on... [more] | DC2020-77 pp.48-53 |
| DC | 2021-02-05 15:55 |
Online | Online | DC2020-78 |
[more] | DC2020-78 pp.54-58 |
| DC | 2021-02-05 16:20 |
Online | Online | DC2020-79 |
[more] | DC2020-79 pp.59-63 |
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